Ann: IMEC Collaboration and Patent Update, page-71

Really positive announcement for me. Haven't seen it mentioned here but the fact they've produced 2 x 23 wafers instead of the single they've produced for previous iterations led me to believe they think they're pretty close and wanted a broader range of tweaks for the final iteration. Hoping I don't have the rose coloured glasses on and am reading too much into it.

Does anyone know what the likelihood of failure is when putting the cells into the Mb chip? Is it a pass/fail, or is there the prospect of it working but reducing performance, requiring further iterations? As someone else said, 4th iteration is unlikely to be the finish line.