Ann: Akida Evaluation Boards Shipment, page-241

Kzhong,

I think the design is pretty well set in concrete - not further iterations needed - we probly went through that in preparing the test chips at the beginning of the year before we made the test chips.

If the test chip meets all requirements, all that is required is to take the individual chip mask from the multi-user wafer for the test wafer and multiply it for a whole wafer. And this is now in the hands of Socionext who are preparing the "tape-out" files for TSMC.

Someone mentioned that we would have the chips by April. Hope they are right.