Ann: Akida Evaluation Boards Shipment, page-246

Hey BarrelSitter cheers for the reply.

From my understanding, the Register Transfer Design entails a simulation of the chip processes to ensure that it is logically correct. From there, Socionext is tasked with the physical design of the chip which may take some time.

Further iterations would address issues regarding the chips physcial design and would occur due to design bugs ( no simulation is 100% accurate to reality ) or due to issues with yield and manufacture tolerance. e.g. there are discrepancies in the performance of chips depending on their distribution on a wafer; typically edge and corner wafers being slower. The design may not work as intended on these edge chips.

Should these issues arise, Socionext would have to review the physical design of the chip and then restart the fabrication process.

Please let me know if I got any of this wrong. I am a relatively new holder, and also new to the chip manufacturing process. Hoping all is smooth sailing for BRN during this process. They're so close now.

Hopefully our understanding the process and its concomitant issues will temper our expectations to account for any delays that may arise as a result of them.