Time to wrap up this first pass at 3D NAND. There are a couple of points which I didn’t get to in the first two posts, which I’ll touch on here. Of particular interest is the relationship of 3D NAND to future post-NAND memory technologies, specifically ReRAM.
Conceptually in many respects, 3D NAND is closer to a post-NAND technology than it is to NAND as we know it today. The slide below from a 2009 Toshiba presentation tells the tale.
From the left, floating gate NAND rolls along to where the path splits with ever smaller NAND geometries above and 3D NAND and other post-NAND technologies below. Other post-NAND include PCRAM, ReRAM, MRAM, etc.
What’s interesting is that 3D NAND is on the post-NAND branch and not on the NAND branch. Apparently this is because for 3D NAND the NAND string is perpendicular to the Silicon Substrate and other post-NAND technologies will depend on a similar three dimensionality.
Another slide from this same Toshiba presentation makes the point a different way.
In the center is the BiCS 3D Technology. Other technologies, including NAND and ReRam surround BiCS as potential extensions of BiCS 3D technology.
The point here is that BiCS technology can be applied to various memories to produce low cost data storage devices. When applied to NAND, the result is 3D BiCS-style NAND. When applied to ReRAM, the result will be 3D BiCS-style ReRAM and so forth.
BiCS is short for Bit-Cost Scalable technology. It is a 3D design strategy and as such allows greater capacity per footprint, which in turn results in lower bit cost. BiCS uses “a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layers to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material.”
Another Toshiba slide from this same presentation graphs the relation between capacity and bit cost. As one would expect, the more layers, the lower the cost. With BiCS, more layers and hence lower costs per bit can be achieved.
BiCS Flash appears to have the potential of a 10 Tbit/ chip.
At the bottom of the slide, Toshiba innocently wonders whether the market would be interested in such “huge” capacity?
Given cloud data center demands today, I doubt anyone is worrying about that one today- If the cost is right.
Toshiba has it right. Future trends will primarily be driven by cost per bit. The technology that will provide the most bits at the lowest cost will succeed.
Cost reduction is the most important issue.
For anyone interested in this Toshiba presentation, here is the link.
3D Resistive Random-Access Memory (RRAM)
RRAM and SanDisk/Toshiba’s 3D R/W technology deserves it’s own post, which hopefully I’ll get to in the not so distant future.
Suffice it to say, that it sure sounds like today SanDisk/Toshiba’s 3D R/W is RRAM.
Yoram apparently said as much at this year’s Flash Memory Summit:
“Further in the future, chip makers including SanDisk are developing 3-D structures that use changes in resistance to create denser chips. But the so-called resistive RAM will require EUV tools, he [Yoram Cedar] said.”
SanDisk has been looking for a new manager for its “3D ReRAM” team since August.
The interrelationship between BiCS 3D NAND and 3D RRAM bears watching.
Toshiba and SanDisk have licensed or otherwise invested in each other’s 3D technologies and today are co-developing both.
In 2008 SanDisk licensed it’s 3D R/W technology to Toshiba.
Then in Q1 2011, SanDisk “made an incremental strategic technology investment with Toshiba that covers a variety of technologies including a three-dimensional NAND architecture, known as Bit Cost Scalable or BiCS, which Toshiba had been developing independently.”
RRAM IP
Many companies have been working on RRAM, for a long time. A very, very long time- which in some respects is a good thing.
Most importantly, the patents on the basic RRAM switching concepts apparently have expired.
The slide below is from a Deepak C. Sekar presentation. Deepak is Chief Scientist at MonolithIC 3D Inc. He also spent almost three years at SanDisk working on both NAND and 3D crosspoint memory.
Deepak makes three points about RRAM IP in the slide above:
Patents, if any, on the basic switching concepts have expired.
Good patents on more advanced concepts exist (eg) Pt-replacement approaches, array architectures, doping, etc.
IP scenario for RRAM a key advantage. Other resistive memories have gate-keepers (eg) Basic patents on PCM, CB-RAM, STT-MRAM fro Ovonyx, Axon Technologies, Grandis.
I suspect SanDisk and Toshiba have a particularly nice hand of good patents on the more advanced RRAM concepts, specifically array architectures.
The slide below is from SanDisk’s 2010 Investor Day.
Eli makes the point that SanDisk holds “Fundamental patents in 3D diode arrays (apply to most 3D approaches)”
I’m going to end with this slide from the IMEC consortium. Its a nice summary showing floating gate NAND, 3D Vertical NAND, and RRAM graphed against Cost/Bit and chip capacity.
Here is the article where the slide above was taken. Apparently Toshiba/SanDisk hasn’t signed up for the collaborative effort.
“IMEC is working collaboratively with major memory manufacturers including Elpida, Hynix, Micron and Samsung on both flash and follow-on memory roadmaps
Toshiba [Sandisk] is a notable absentee from the program.”
There could be many reasons why Toshiba/SanDisk wouldn’t be interested in working with IMEC.
One would be that Toshiba/SanDisk feel they have the inside track on the roadmap.
