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Ann: Results of Meeting, page-50

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    some stuff I just heard from my audio recording I listened to from AGM – this is just the formal preso (question time – I wasn’t there for all of it Ill send through most likely on the weekend)

    Fred - confirmed will be in mass production by end of year
    Danny - said the same as his opening statement
    - confirmed they have reduced the manufacturing timeframe from 20 weeks from the beginning of this year down to 6 for the transducer
    - confirmed they are very pleased to confirm the software they have developed not only aids design but tolerances on different materials used. He said they have been trying to do this for years and have now been able to deliver it.
    - secure capacity for mems transducer and ASIC but still getting over packaging issues as others have already commented.

    Yuval then spoke
    - spoke broadly about this new tool, thermal effects, voltages, and more importantly physics around acoustics. before relying on experiments and trail and error essentially. software tool (one of them called - Console! for micro acoustics - wasnt exactly clear)
    - pixel is now square not round (this is a change this year) - gives benefits of automatically knowing what each change will deliver.
    - round is easier to calculate acoustics but square was better and these new tools allowed this change to occur without months and months of delay - he didn't elaborate why, maybe the slicing up of the chip
    - before a change in the structure would cause the need to complete 600 different variants to see what would be the impact to all layers, now this is not needed.
    - took a few months to configure the tool but now they can setup variations 1 or 2 a day and then if the trend of the variable (can play with 30 variables) isn't producing they can stop going down that path.
    -2019 - first sound coming from chip which was from a commercially viable process
    - 2020 - demonstrate from best chips we had down to 100 htz (spl of the simplified structure was low down to 45- 50 DBs) single pixel. was in cleanroom and the noise of the cleanroom was up to 40 DBS, so they couldn't really measure anything
    - early 2021 - get SPL up by 5 DBs, but have done simulation results which will get it up another 10-15 above this. They have tested it through the software but yet to do the run on this variable. so from this 65-70 looks like what a single chip will deliver.
    - first quarter played chips outside clean room. demo chips outside multiple chips (4 chips) on a board
    - working on 80 chip board
    - later this year complete chips with this optimised at the new level ready for production
    - audio pixel, analog can't cover the range of low frequencies, 1 chip most of the range, 2-4 chips, all of the range
    - tool developed to show customer what configuration is needed for what type of application, it selects chips, directs sound etc
    - packaging is still a problem. more than 100 wire bonds which cannot be done manually and only bigger packaging houses can get done. Vendor in israel trying to condense years on development into a few months.
    - can save time in this process for packaging and fix within 6 months
    - worked on asic first in 2013. 2016 first gen working in 2016. second gen in 2020. because the first ASIC generation didnt work on the simplified structure. this was because of the pixel health programming and design. new design complete in jan/feb and they are being tested by the vendor and then Audio Pixels will then get them.
    - inhouse capabilities improved, first generation board was via the probing station, now they have a one and four chip tester while packaged. prober was a bottleneck as you had to run one test at a time. have 6 of these out of clean room testing boards now.
    - FPGA chip is what is driving 80 chip board. Thats what that linkedin programming job was for. first board had issues and hence they are now working on a new generation board to demonstrate all different configuration.
    - new wafer prober, original prober was for undiced wafer, new one was for diced wafer. last year process was a few minutes manual process to test, now system can align on each chip diced automatically.
    - also designed manual prober because because some tests are quite long, sometime for days or weeks , easier to build, cheaper (normal prober 1/2million), these new probers only cost $10,000. much better for reliability

    ends with, sound pressures getter higher and will get higher in coming months, still focusing on end of year for mass production. Still some bottle necks in the production line which I have not disclosed but this will be fixed in the next iteration already sent to the fab.

    That was the end of the formal presentation and went to question time.

 
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