@AM27Well I AM27, I AM8tey and I reckon the company plays more games than Tiger Woods when issuing releases..
As we can see the wafers scheduled v those received is enough to make you wonder if anyone at IMEC/HGST/4DS can count?
Such ambiguity is either incompetence or designed to confuse one might suspect and therefore the first platform lot of 18 is the same as the typo of 12 in the second platform lot, or the second platform lot of 12 was enough for the partners to then run a another 6 down the line to achieve their goal of manufacturing a fully functioning memory chip....
We don't know because nothing states that IMEC developed the extra 6 or HGST did on their commercial platform?
But IMEC definitely produced the 3rd non platform lot on their commercial production equipment bench so I am quietly confident at this stage.
Guess the "Technical Update" due in a couple of days will shed light, or perhaps not... ;-)
But ol 8teys got his forks ready so bring it on.... hehehe
3-10-2019
During August and September 2019, the Company received and analysed the two sets of twenty-three 300mm wafers
(46 in total) in Lot 4. This analysis, and the accumulated knowledge from prior Lots, has: affirmed the impact of changes in process conditions on cell structure and desired memory characteristics for stand-alone Storage Class Memory (1)
(1 Notably speed, endurance and retention.)
Based on the results of Lot 4, the Company and imec have agreed to integrate 4DS’s memory with imec’s megabit platform – a significant milestone as 4DS moves towards its goal of demonstrating a 1 megabit memory chip
29-10-2019
4DS and imec have commenced planning for the initial phase of the integration of 4DS’ memory with imec’s megabitplatform.
Chief Executive Officer and Managing Director, Dr Guido Arnout, attended the invitation only “9th International Workshop on
RRAM/MRAM” organised by imec and Stanford University that was held at imec’s facilities on 17 and 18 October 2019.
Dr Arnout commented "Attendance at the workshop reaffirmed our long term belief that 4DS' Interface Switching ReRAM is unique in the ReRAM field.
Our goal to develop Storage Class Memory close to DRAM remains an industry priority.
28-11-2019
The Company is also pleased to report that 4DS and imec have commenced production of the
initial lot of 300mm wafers for integration of 4DS’ memory with imec’s megabit memory platform.
30-01-2020 Company expects to receive this
first full set of
(18) wafers integrated with the imec megabit platform within a fortnight,barring any unforeseen circumstances
24-06-2020
Completed analysis of the “Initial Platform Lot”, fabricated prior to HGST joining the 4DS/imec collaboration. The Initial Platform Lot was focused on integration of 4DS’ memory and imec’s megabit platform and has enhanced 4DS’ understanding of, and validated, the process steps required.
A set of 300mm Additional Wafers Lot.. On 24 June 2020, 4DS announced the results of its analysis of the Additional Wafers Lot (being the First Non Platform Lot of 300mm wafers). The First Non-Platform Lot was fabricated with process condition contributions from Western Digital and imec.
10-08-2020
Future Development. The additional wafer lot results formed the basis of discussions on development strategies which need to be undertaken over the next six months to put the Company in a position to potentially deliver a megabit chip and/or a corporate transaction during 2021. As such, the Company now proposes to start fabrication of two sets of wafers this quarter on imec production equipment. imec will manufacture one lot of twenty-three
(23) Non-Platform Wafers (
Second Non-Platform Lot) and one lot of twelve
(12) Platform Wafers (
Second Platform Lot).
28-10-2020
4DS is pleased to advise that imec has commenced the manufacture of twenty-three
(23) Non-Platform Wafers (
Second Non-Platform Lot) and one lot of twelve
(12) Platform Wafers (
Second Platform Lot).
As stated in 4DS’ announcement dated 10 August 2020:
• the
Second Non-Platform Lot wafers are less complex, faster to fabricate, and easier to test than Platform Wafers, yet can provide valuable input on which process conditions exhibit the biggest improvements in speed, endurance and retention; and
• following consultation with imec and Western Digital, the
Second Platform Lot wafers are being fabricated so as to contain dense memory arrays with transistors that are able to select memory cells. Based on the results from the above two wafer lots, 4DS and its partners will potentially progress to fabricate wafers with all the control logic necessary to read and write selected bits and bytes, and therefore be able to operate as
a fully functional megabit memory.Timing Remains on Track Barring any unforeseen equipment problems or new COVID-19 government ordinances:
• the
Second Non-Platform Lot wafers should be available for analysis in mid to late Q4 2020; and
• the
Second Platform Lot wafers are expected to be available for testing in early Q1 2021.
The results from both wafer lots will define the Company’s 2021 strategic development plan to achieve its goal of fabrication of a megabit chip and/or a corporate transaction.
1-02-2021
Further to the update provided in the Company’s Quarterly Activity Report dated 20 January 2021, 4DS confirms that it has now completed its testing of the
Second Non-Platform Lot. significantly,
19 of the 21 device wafers were functional, a first for the Company (the two nonfunctional wafers were the result of being manufactured outside the imec process window);
27-01-2021
The
Second Platform Lot is using imec’s memory platform, and contains dense memory arrays with the control logic necessary to read and write selected bits and bytes. Production of the
Second Platform Lot commenced at imec on 27 January 2021
21-06-2021
As previously advised during the quarter imec were finalising the production of the
Second Platform Lot and 4DS is pleased to advise eighteen
(18) wafers have now been received at its Fremont facilities
The Company also took the opportunity to utilise spare capacity on imec state-of-the-art
commercial production equipment to manufacture a
Third Non-Platform Lot comprising of twenty-three
(23) wafers. This decision was undertaken to ensure the Company continues to build an extensive data set around the process parameters for its Interface Switching ReRAM technology.
