Ann: Extension of Voluntary Suspension, page-417

Thanks@Xander98 for the article.

From article:
https://www.ednasia.com/4ds-reram-speeds-up-to-dram-spec/

"After extensive measurements and analysis of its ReRAM cells fabricated in different sizes, 4DS concluded that cell currents needed to be boosted by an order of magnitude to reach DRAM latency at the cell size targeted by the industry for storage class memory, said Arnout.However, a short cell latency is still insufficient, he said. The latency that matters is the sum of the inherent memory latency and the time required to detect and correct any read errors, through error correction circuitry (ECC) necessary to reliably detect the state of ReRAM cells over time. Arnout said other ReRAM, including filamentary and CBRAM, for example, have struggled with the high bit error rates. Filamentary ReRAM technologies essentially switch at a single point making them susceptible to irregularities in the switching region, so even small changes will result in very large current changes.4DS' Interface Switching technology, however, reduces the influence of random irregularities within the switching region, thereby minimizing current fluctuations. Essentially, said Arnout, latency of the company's Interface Switching ReRAM is dominated by the inherent memory latency and not by the time overhead of error correction."

On 17/08/21 announcement:

"Third Non-Platform Lot wafers yielded an order of magnitude decrease in cell on-resistance, which
translates into an up to one order of magnitude boost in read speed"

Just want to get an opinion on this, we were "comparable" at 2017, now we are as quick as DRAM, or we are quicker than DRAM?