4DS - Anything but Charting, page-24297

PL3 will deliver megabit chips - array + transistors + control logic.

Fully functional as a standalone memory chip that 4DS can run testing programs on to determine "real world" performance and publish metrics to an industry agreed standard.

4DS have already been able to fab prototype kilobit arrays in their own lab, which met IMEC's criteria for development.

IMEC is all about developing an industry compatible process on state of the art equipment. In theory, performance should be better and more consistent between chips, because you can manufacture to much tighter tolerances in an industrial fab.

A further PL4 has already been flagged - the objectives of which have not been discussed yet. My speculation is (assuming this lot is successful and doesn't require additional rectifications) they will look to fab a lot that sacrifices speed for retention and/or endurance - so that the flexibility of the tech can be demonstrated. The other possible thing they could do is chase speed as far as they can. Maybe they will split the lot to produce a range of metrics within the Speed/Retention/Endurance map.