4DS MEMORY LIMITED (ASX:4DS) - 4DS - Anything but Charting, page-24319 - HotCopper | ASX Share Prices, Stock Market & Share Trading Forum

Originally posted by Hateful8: ↑

Hey Brother, I believe the ref to Samsung pic extract shown was taken from one of the slide pack sheets from this Mob...

3D Monolithic Resitive RAM (osti.gov)

Matt Marinella & a group of other industry think tank type propellor heads spent a number of years getting together to work out how to approach a lot of the questions we see being asked of the industry today as it grapples with scaling density, AI, $ cost & power useage...

You can see that Samsung has been in the hen house for 10-11 yrs or so now, along with Stanford U & of course IMEC... So how you F... something up after 10 yrs of stuffing around with the design is still a question I'd like to understand a little better but will accept that what supposedly happened, happened.

As for the need? It is simply one of end of effective design life for old tech that fails to adequately address both Moores Law & Von Neumanns bottleneck & chews a lot of power in doing so...

Going to next gen means being bigger, denser & faster whilst using less power and that is the key here.. Be it Nand or a non-vol Dram application, it needs to stack and it needs to meet the req of the future outlook challenge in the last slide..

4DS has, we believe, now done this with the uniformity / endurance degradation issue sorted...

Imec/Stanford/Samsung seem to have all contributed to a 3D variant other than cross point because in the same way F1 technology leads modern car design, so to does high speed computing lead the laptop... And the world now demands bigger better faster performance for life online and also for living on the edge... AI

5-10 yrs ago it was written soon it will be foretold.. 8tey

Key Future Applications:
– 3D ReRAM Storage Class Memory (5-10 yrs) ... Which as we know is tuned for either Memory & Storage = Mobile & the Cloud
– Beyond Exascale computing; neural computing

Problem: neural algorithm training requires significant memory and logic interaction
• What is the most efficient way to combine memory, logic and interconnects?
• SRAM: on chip cache memory is limited to ~40MB digital (Intel E7)
– ns latency, max regardless of CPU, GPU or ASIC
• Off chip communication to DRAM costs >100 pJ/op, ~10ns latency
Answer
• Resistive memory on chip: can be stacked to >TB/cm >100 layers
– On chip access, <pJ per op and <1ns latency possible
– Terabit densities on single chip – on chip wiring is low energy!

• Significant power savings using a ReRAM based HW accelerator
– Reports of as high as 10^8x energy efficiency over CPU-based system
• Also: 3D layering of memory considered
“biology inspired”

Expand

Thanks 8tey,

I was thinking of a more unexpected use of tha 4DS technology.

A special memomry for the DoD, for example.

Until 2017, KH was president of Memoright International which had some contratcs with US Defense

But maybe there is no need to look at other uses.
Polecam could be right and they managed to use imec EUV to show that a 4DS cels array can be verticaly stacked
Wich will mean a low cost process.

The holy grail !

But still not sure that the etching problem was entirely solved.
imo, they met this problem when trying to punch holes through several electrode layers. There is always a residue problem when they do that.

I tend to think that they decided that this problem could solved later and that the technology - as it is - was good enough to be sold or to attract some new developpment partner.

All speculation, of course.