Sorry, I am going to have to again disagree.
The issue you point out with regards to Platform 3 is by no means a fundamental technology issue. 4DS Memory while focused on resolving the etch residue issue added new process conditions that simply do not work. What you need to look at is Platform 2 and use that as a base for what we can expect moving forward. Platform 3 was a disaster / total write-off.
Base process conditions from Platform 2 and research completed at Stanford post Platform 3; would have allowed 4DS to find that optimum needed to achieve a fully functioning Non-Filament Interface Switching ReRAM Megabit chip with zero defects.
Platform 2 - Confirms the Following
#New process breakthroughs have made 4DS’ Interface Switching ReRAM technology fully compatible with state-of-the-art high-volume DRAM and NAND production processes
#Second Platform Lot wafers demonstrated scalability of its memory cell to the smallest cell geometries supported on imec’s memory platform / 300mm wafers using state-of-the-art process equipment
#Second Platform Lot wafers demonstrated memory cell switching using an access device which is a critical step for producing a functional megabit memory array
The below announcement would have never been made if a megabit chip was not achievable.
