My comments related to the description of
high chip stacking.
It sounded more like they were trying to high-stack digital MEMS multiples the same way that chips are stacked in 3D devices e.g.
https://en.wikipedia.org/wiki/Three-dimensional_integrated_circuithttps://en.wikipedia.org/wiki/System_in_a_packagehttps://en.wikipedia.org/wiki/Multi-chip_modulehttps://en.wikipedia.org/wiki/File:Wireless_TSV_(model).PNG
"... The invention discloses a chip packaging structure, a loudspeaker and a chip packaging method, and relates to the technical field of chip packaging to solve the problem of
high chip stacking. ..."
The diagram in the posted patent shows the ASIC mounted in the cavity and the MEMS mounted above it in an offset location.
If they are only stacking an ASIC as one chip and the MEMS as a second chip on top of the first then that would be an appropriate way of mounting both devices into a smaller footprint onto a substrate. But that substrate is then thicker than the original chip with the ASIC and the MEMS side-by-side. If the cavities are comparable in size to the MEMS on its own then an array of chips could take up less room, true. But the dividers between the cavities may still add up to a similar area overall. It just looks tidier if it is a grid. But the idea of these chips is that they can be mounted on any PC board in any multiple, and in any configuration. If it attempts to stack chips in a higher number multiple, which I agree that I initially thought they were attempting, my comments are still pertinent.
Either way it means a completely different chip packaging construction to what we have seen previously. But if it works and is practically superior from the point of selling the chips I'm certainly not going to argue.
(20min delay)