@darrenrr
plenty in there
funny what fills the vacuum lately when there is zero communication -
60nm to 20nm jumps 40nm to expedite time constraints / impositions
PL4 data solid but 'variables' are present
PL5 simulation prior to run to optimise 'process' to gain 'manufacturing improvements ( yield/ defect density & parametric data etc etc ) that simulation hypothesis outcome clarifies 'variables' ('variations and experiments ' - PHs words)
the numbers on that simulation by definition would be expected to also deliver operational dynamics in line with PL4 at the least...(consistency as ph keeps saying)
PL5 run and delivered - outcome unknown to joe citizen but 'real time' may have delivered some 'process' improvement data appropriate to 20nm - it also seems the universal platform cannot get a total read so 'variables' of one sort or another remain - punters need to remember issue causation is not specified
Infineon engaged design only contract for area/cell access platform specific to 4ds memory to read the total memory area
this is an NRE engagement - ie payment for design solution - cost seems reasonable and aligned to current industry practice - it is a fee for service agreement nothing more
the design solution contract to include test chip ( 'test memory array or chip' - PHs words)
( i get the feeling they were hoping off the back of good PL5 data and total read to go straight to asic macro for either IC or stand alone memory - possibly with infineon as they seem to have been in the loop for a while - and PL5 non read/universal platform issues have altered the pathway a little yet again - cart before the horse really as you need 20 out of the box)
safe to say PL5 has delivered data of some sort and the market is yet to be informed
safe to say the market sees significant reintroduced risk in the absence of PL5 news, the remaining cash runway and the way events have unfolded in the recent past
just more speculation nothing more as success on PL6 remains the gateway forward
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