The take home message about PL5 seems to be that they uncovered processing adversity in relation to the memory cell stack & have since changed some processes (which they've called optimisations) "just in time for the Sixth Platform Lot" (which is very fortuitous timing) & they're hoping the optimisations will successfully address (fix) the processing adversity that's been uncovered in PL5, so that PL6 @ 20nm has a better chance of being a manufacture & test success...
4DS Price at posting:
4.9¢ Sentiment: None Disclosure: Held
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