With regards to the shortfalls, there are obvious interoperability challenges using 4DS technology on imec’s universal platform vehicle. I strongly suspect this was known during Dr WvdH tenure.
Considering we have demonstrated a fully functional megabit array on Platform 4 @ 60nm, the shortfalls identified may appear to be limiting further performance gains as we scale down to smaller nodes.
Unfortunately, without 4DS Memory clearly explaining specific shortfalls related to imec’s platform, we are left to speculate. This lack of transparency is frustrating, as it continually forces us to guess what should be known. That being said, it’s evident these interoperability challenges is the key driver behind the Infineon design agreement to commercialise our proven technology without the shortfalls experienced using imec’s platform and unlock our full potential.
At the AGM, Ting’s focus was squarely on successfully delivering a fully functional Platform 6. Ting emphasised that Platform 5 was a segway and he needed to see certain ingredients in Platform 5 before he can proceed to Platform 6.
I would not put too much into Platform 5, it’s all about Platform 6 which is likely what will be moved to Infineon to design a 20nm chip for commercialisation.
Not sure if this answers your question, just finished work.
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