Ann: 4DS Memory Successfully Completes Fifth Platform Lot, page-19

So they have:
1) Clarified that PL5 was not for the purposes of optimising the memory cell and was only for learnings in fabrication of thee 20nm memory stack - implying that we will never receive any "interim results".
2) Clarified that PL6 timeline has been delayed which is basically stating the obvious - but based on the fact its not limited to Q1 2025 and is instead 1H 2025, I'd even speculate that they started PL6 from scratch once they "learned" from PL5.

No clarification on the agreement with imec which has expired. So are imec doing this work at the inclusive costs we've already paid? And lets remind everyone what the original timelines were.