1S1R backend ots ( selector) GSSN with HfO2 oxram device ... the issue About one order of magnitude improvement in terms of memory density can be achieved with 1S1R with respect to conventional 1T1R architectures.[18]However, RRAM co-integration with a back-end selector implies several challenges. First, the process integration complexity increases. Second, achieving high memory capacity while preserving reduced electrical consumption becomes challenging due to a trade-off between programming voltages and leakage currents. Third, to achieve high precision on device resistive states implies a degradation of its programming endurance capabilities due to a trade-off between memory window and endurance capabilities.
solution To deal with those challenges, a specific design of both memory stack and applied programming conditions for the application of interest is required.[19–22] In this context, the co-integration of an HfO2-based OxRAM device with an ovonic threshold switch (OTS) selector on single memristor crossbar arrays to implement the BSNN synaptic weights (Figure 1B)) is proposed. OTS co-integration with HfO2-based OxRAM has been satisfactorily demonstrated in the previous years.[18,20–23] Through stack design and applied programming conditions adaptation, the 1S1R dynamic switching capabilities have been elucidated, the 1S1R binarized window margin optimized, and its programming endurance capabilities enlarged.[22] In particular, the 1S1R pertinence for standard low-precision synaptic weight encoding during network training on-chip has been demonstrated.[18]
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