Hey legends.
Love reading your thoughts. Have held this for over three years riding with a few of you.
So do you think this is the wafers being completed as opposed to the wafers being joined to asic driver?
From memory the major hurdle is the later part... When that happens we will be out of the lab and into the device so to speak. Or is this a I want it to be and the wafer asic driver combination ...
Cheers.
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