Ann: IMEC Collaboration and Patent Update, page-167

"Once these wafers have been manufactured, they will be analysed by both IMEC and 4DS in order to identify the wafer that exhibits the best endurance and retention characteristics. Results are expected in 3Q19 (September quarter).At that time 4DS will decide whether the specs of the memory cells on that particular wafer in lot 4 are sufficient to move to the next stage of development or if a fifth iteration is required.

Next step is to integrate with IMEC’s memory platform. If iteration 4 is indeed the last one, the next step will be to integrate the Interface Switching ReRAM chip with IMEC’s 1 megabit memory platform. This platform is essentially an off-the-shelf design in IMEC’s library that will be used as a carrier for 4DS’ 1 megabit Interface Switching ReRAM chip, including connectivity to the outside world.

While 4DS hasn’t announced an expected timeline for this integration phase, we believe this process is relatively straightforward compared to the development work done to date and may potentially be completed in 1HY20.

Once the integration is completed,4DS will collect statistically significant and meaningful data on yield, endurance, speed and data retention, essential for high-volume memory manufacturers (such as SK Hynix, Samsung, Intel, SanDisk(owned by Western Digital) and Micron) in their decision-making process around licensing or potentially acquiring 4DS’ technology, which we believe may happen in 2020"

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