"Rather than alter the fabrication process in order to try to diminish or possibly eliminate the slightimperfections of fabrication, the company together with its vendor devised a plan that will revert thespecification to compliancy, while diminishing dependencies on the vendor’s fabrication tolerances.Considerations concerning preservation of intellectual property protection prohibit discussion in greaterdetail, however management is confident that the relative nuanced changes that are already in progresson test wafers that are anticipated to be completed by mid-September 2019, will produce the desiredresults with minimal disruption to the overall fabrication pipeline.
Accomplishing the aforementioned milestone has allowed the company to authorize larger scale waferproduction, and reinvigorate our interaction with our packaging vendor in anticipation of receiving largerquantities of wafers. It should also be noted that all testing conducted for the entire period has been doneutilizing our proprietary ASIC and algorithms."
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