Some of the most interesting places to study in our solar system are found in the most inhospitable environments – but landing on any planetary body is already a risky proposition. With NASA planning robotic and crewed missions to new locations on the Moon and Mars, avoiding landing on the steep slope of a crater or in a boulder field is critical to helping ensure a safe touch down for surface exploration of other worlds. In order to improve landing safety, NASA is developing and testing a suite of precise landing and hazard-avoidance technologies.
Future NASA human spaceflight and robotic science missions will require more powerful space-based computing for autonomy, high-data-rate instruments, and human-robotic interactions.
Credits: NASA
NASA’s High Performance Spaceflight Computing (HPSC) project is developing a flight computing technologies that will provide at least 100 times the computational capacity compared to current spaceflight computers. The HPSC project will deliver newly designed multicore computing chips with multiple processing cores on each chip, bundled with operating software to run them. A team of engineers from NASA’s Jet Propulsion Laboratory are formulating the HPSC development approach. This NASA team will provide technical management of the design and delivery of the computing chips.
Current space-qualified computing technology must be configured around the part of a mission that requires the most power – a practice which targets mission success but leads to inefficient use of resources over the lifetime of a mission. For example, a Mars surface mission has extreme needs for high-speed data movement and intense calculation, as well as stringent fault tolerance, during the planetary landing sequence. The flight computer must be configured to meet these needs, which draws significant power and other resources. However, once safely landed, routine mobility and science operations may rarely need that same level of capability, at least not in a sustained manner. Nighttime operations can require even less resources. HPSC’s improved design offer the flexibility for the computing processing power to ebb and flow depending on the mission and operational requirements. This will save a large amount of energy and improve overall computing efficiency.
Because of this energy savings and increased computing efficiency, this high-performing computing chip will benefit many areas of spaceflight operations, including extreme terrain landing, managing a vehicle’s health, automated guidance, navigation and control, autonomous and telerobotic construction, and more. Because all types of NASA missions require computing capabilities, this updated chip could benefit all of NASA’s future undertakings, from earth science missions, to deep space missions, to human spaceflight.
The HPSC team is working to finalize the architecture and design, processor technology, and production and commercialization approach for the chips, and to prepare for demonstrations on space platforms and lunar landers. The chips are expected to be available in the 2023-2024 timeframe, and planned to be incorporated into single-board computers shortly after. The overall HPSC project is managed by NASA’s Jet Propulsion Laboratory (JPL), with single board computing design being accomplished by NASA’s Goddard Space Flight Center (GSFC) in Greenbelt, Maryland, and NASA’s Johnson Space Center (JSC) in Houston, Texas. Additionally, the United States Air Force Research Laboratory (AFRL).
Future NASA space mission scenarios require an improved computing system with significantly expanded computational performance and more efficient use of energy. HPSC will achieve these spaceflight computing needs over the next two decades, offering unprecedented opportunity for future advancements and upgrades in a flight computing system.
Partners:
- Boeing Defense, Space and Security (BDS) out of El Segundo, CA, is developing prototype Chiplet devices including packaged parts and bare die, a Chiplet behavioural model, Chiplet Evaluation Boards and System Software.
- The USC Information Sciences Institute is providing system software development support.
- The University of Michigan is providing ARM processor expertise.
PRINCIPAL TECHNOLOGIST
Stephen Horan
[email protected]
PROJECT MANAGER
Rich Doyle
[email protected]
NASA Langley Research Center
https://www.nasa.gov/press-release/goddard/2017/nasa-selects-high-performance-spaceflight-computing-hpsc-processor-contractor
This is a cost-plus fixed-fee contract with a total contract value of $26.6 million which includes five options to enhance the capability of the Chiplet, increasing its processing performance, providing additional interfaces and improving the robustness of the Chiplet packaging. The period of performance is from March 27, 2017 through Dec 23, 2020.
Boeing will provide prototype radiation hardened multi-core computing processor Chiplets, system software which will operate on them, and evaluation boards to allow Chiplet test and characterization. The Chiplets each contain eight general purpose processing cores in a dual quad-core configuration, along with interfaces to memory and peripheral devices,
and will have the flexibility to tailor performance, power consumption, and fault tolerance to meet widely varying mission needs.
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