2021 BRN Discussion, page-247

This is the Vorago

Under the Heading

Silicon Space Technology Corporation
1501 South MoPac Expressway, Suite 350
Austin, TX 78746
(512) 347-1800

https://sbir.nasa.gov/SBIR/abstracts/20/sbir/phase1/SBIR-20-1-H6.22-4509.html


PROPOSAL NUMBER:
20-1- H6.22-4509
SUBTOPIC TITLE:
Deep Neural Net and Neuromorphic Processors for In-Space Autonomy and Cognition
PROPOSAL TITLE:
CNN RNN Processor



The ultimate goal of this project is to create a radiation-hardened Neural Network suitable for Ede use. Neural Networks operating at the Edge will need to perform Continuous Learning and Few-shot/One-shot Learning with very low energy requirements, as will NN operation. Spiking Neural Networks (SNNs) provide the architectural framework to enable Edge operation and Continuous Learning. SNNs are event-driven and represent events as a spike or a train of spikes. Because of the sparsity of their data representation, the amount of processing Neural Networks need to do for the same stimulus can be significantly less than conventional Convolutional Neural Networks (CNNs), much like a human brain. To function in Space and in other extreme Edge environments, Neural Networks, including SNNs, must be made rad-hard.
Brainchip’s Akida Event Domain Neural Processor (www.brainchipinc.com) offers native support for SNNs. Brainchip has been able to drive power consumption down to about 3 pJ per synaptic operation in their 28nm Si implementation. The Akida Development Environment (ADE) uses industry-standard development tools Tensorflow and Keras to allow easy simulation of its IP.
Phase I is the first step towards creating radiation-hardened Edge AI capability. We plan to use the Akida Neural Processor architecture and, in Phase I, will:

1. Understand the operation of Brainchip’s IP
2. Understand 28nm instantiation of that IP (Akida)
3. Evaluate radiation vulnerability of different parts of the IP through the Akida Development Environment
4. Define architecture of target IC
5. Define how HARDSIL® will be used to harden each chosen IP block
6. Choose a target CMOS node (likely 28nm) and create a plan to design and fabricate the IC in that node, including defining the HARDSIL® process modules for this baseline process
7. Define the radiation testing plan to establish the radiation robustness of the IC
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