He doesn't need to RussellB01
its been posted here multiple times - you really have to understand the IP implications to the Use of 'Art' and how it is licensed through the semiconductor industry though don't you.
To believe the IP is vulnerable due to collaborative agreements and royalty payments is extremely naïve and generally misinformed in 2021.
Interestingly it was suggested to Intel at the time that they take up ' Rices ' product licences / patents and proceed to manufacturing with it - they declined as they did not believe in the technology (porous silicon oxide) would be a useful technology .....one of many missteps they made at the time.
Plenty on the web about the joint Leti / WBT shared IP
collaboration also - available to all
Thetechnology that Weebit uses was developed from James Tours research. The majorbreakthrough in this research was being able to use silicon oxide as theswitching material in ReRAM. Originally James Tour’s research was funded by Sandisk, but they didn’t believe that they hadcreated a silicon oxide switch and pulled their funding. James Tour and Riceuniversity then took their discoveries patented them.
Rice university Patents
Siliconoxide based memresistive device
https://www.google.com/patents/US8592791
Frompatent: Silicon oxides,particularly silicon dioxide (SiO2) have long been considered to be a passive,insulating component in the construction of electronic devices. However, in theembodiments presented herein, it is shown that silicon oxides (e.g., SiO2 andSiOx) may serve as the active switching material and electron transport elementin electronic devices upon being converted into a switchably conductive state.
In summary, theelectronic devices disclosed herein have advantages that are among thefollowing:
·Non-volatility: Once written or erased, the memory state remainswhen unbiased (i.e., there is no current flowing) for an indefinite amount oftime
·Two-terminal structure: The write, erase, and read functions ofthe present electronic devices share the same electrodes in a two-terminalconfiguration, allowing for increased ease of miniaturization over thethree-terminal structure of conventional transistors.
·Nondestructive reading endurance: The reading voltage used doesnot affect the stored memory states, if the reading voltage is below a certainlevel. Reading endurance shows no degradation after 10,000 continuous readingcycles for both ON and OFF states.
·Non-charge based memory state: No degradation was observed forthe stored memory states after X-Ray, heavy ion and proton radiation exposure,demonstrating the non-charge based nature of the electronic devices and theirpotential use in radiation hardened electronics.
·Improved ON/OFF ratio: High ON/OFF ratios of up to 106 orgreater can be achieved, particularly after further miniturization.
·Fast switching time: Pulse widths of ˜1 μs and lower may be usedfor the writing/erasing operations.
·Potential high density: The two-terminal nature and small sizesof the electronic devices potentially allow compact 2-D and 3-D memory arraysto be constructed.
·Compatibility with CMOS technology: The structure and materialsare fully compatible with standard CMOS technology.
Thebenefits of Silicon oxide are discussed by James Tour here:
“Silicon oxide isabundant, it is sand. There is plenty of it and it is non toxic. Silicon oxideis the best known material in the world studied more than any other material inthe world. It has had over a trillion dollars and over a million person yearsinvested into it because all of the silicon industry runs on silicon, siliconoxide interfaces. The reason we use silicon is because it can grow a stableoxide and we know how to control its growth. So, we know a lot about thematerial there is no retooling. We have chosen the material that works best.”
Relatedpapers
·Yao, J.; Zhong, L.; Natelson, D.; Tour, J. M. Insitu Imaging of the Conducting Filament in a Silicon Oxide ResistiveSwitch. Nature Scientific Reports 2012, 2:242, 1-5.
https://www.researchgate.net/publication/221852532_In_Situ_Imaging_of_the_Conducting_Filament_in_a_Silicon_Oxide_Resistive_Switch
·Yao, J.; Zhong, L.; Natelson, D.; Tour, J. M. IntrinsicResistive Switching and Memory Effects in Silicon Oxide. Appl. Phys.A 2011, 102, 835-839.https://www.researchgate.net/publication/225826058_Intrinsic_resistive_switching_and_memory_effects_in_silicon_oxide
·Yao, J.; Zhong, L.; Natelson, D.; Tour, J. M. Silicon Oxide: ANon-innocent Surface for Molecular Electronics and NanoelectronicsStudies. J. Am. Chem. Soc. 2011, 133, 941-948.
https://www.researchgate.net/publication/49699499_Silicon_Oxide_A_Non-innocent_Surface_for_Molecular_Electronics_and_Nanoelectronics_Studies
Porous siox materials for improvement in siox switchingdevice performances
From patent: Despite great switching properties in SiOxunipolar memory, the switching properties have two limitations:
- few endurance cycles (~ 1000 cycles)
- high electroforming voltage (> 20 V). The above deficiencies can be obviated by using a porous SiOx. New RRAM memory structures employing a nanoporous (NP) silicon oxide (SiOx) material are discussed herein, which enables unipolar switching through an internal vertical-nanogap in the NP silicon oxide rather than an edge.
Somebenefits of porous silicon oxide mentioned in the patent:
- the porous material reduced the forming voltage—the power needed to form conduction pathways—to less than two volts, a 13-fold improvement over the team's previous best and a number that stacks up against competing RRAM technologies
- the porous silicon oxide also allowed the elimination of the need for a "device edge structure. That means it can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges,
Tour said. "When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that."
- porous silicon oxide material increased the endurance cycles more than 100 times as compared with previous nonporous silicon oxide memories.
- the porous silicon oxide material has a capacity of up to nine bits per cell that is highest number among oxide-based memories, and the multiple capacity is unaffected by high temperatures.
SiOxBased Invisible / Transparent Nonvolatile Memory
PCT/US2012/025435
http://www.google.com/patents/WO2012112769A1?cl=en
https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2012112769&redirectedID=true
FromPatent: Invisible/transparent nonvolatile memory devices are discussed herein.More particularly, memory devices that are transparent regardless of memorydensity are provided herein. If transparent materials are utilized for theentire design, then the entire memory would be transparent, regardless of thedensity.
Myunderstanding: Transparent memory devices may allow the development oftransparent electronics. With transparent memory you can, for example:
·havememory embedded within glass, i.e. make glass smart,
·useit for exotic new devices like transparent flexible memory chips
·useit to built on top of plastic, so it can even be part of the coating you’relooking at through the screen.
Related papers:
·Yao, J.; Lin, J.; Dai, Y.; Ruan, G.; Yan,Z.; Li, L.; Zhong, L.; Natelson, D.; Tour, J. M. Highly Transparent NonvolatileResistive Memory Devices from Silicon Oxide and Graphene. NatureCommun. 2012, 3, 1-8.
https://www.researchgate.net/profile/Jian_Lin7/publication/231863722_Highly_transparent_nonvolatile_resistive_memory_devices_from_silicon_oxide_and_graphene/links/00b495373dbf4b81c9000000.pdf
Other
·PCT/US2011/050812
“SiOx BasedNonvolatile Memory Architecture”
http://www.google.com/patents/WO2012071100A1?cl=en
https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2012071100&redirectedID=true
·PCT/US2012/052450
Addressable SiOx Memory Array with Incorporated Diodes”
https://www.google.com.mx/patents/WO2013032983A1?cl=en
https://patents.google.com/patent/US9385163B2
https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2013032983&redirectedID=true
·USPat. 8,390,326
“Method for Fabrication of a Semiconductor Element and Structure Thereof”
http://www.google.com/patents/US8390326
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8390326.PN.&OS=PN/8390326&RS=PN/8390326
·https://patents.google.com/patent/US7973559
Weebit’s memory chips also received a‘Hard-Rad’ status from NASA, meaning they are “impervious to the effects ofradiation”. This is important for storage needs in satellite, military andsimilar niches.
https://hotcopper.com.au/threads/weebit-patents-and-media-exposure.2673127/
https://hotcopper.com.au/threads/discussion-on-patents.2744786/
Weebit patents with Leti
·WeebitNano and Leti filed two new patents optimising ReRAM performance.Electrical performance means the device behaviour in a product and theimportance of these patents are the ability of the device to meet the specifiedrequirements over time.
·WeebitNano and Leti filed three new patents for improved yield and reliability ofadvanced ReRAM products.
Weebit license agreement with Rice University
On the 21st of December 2018, the licenseagreement between Rice University and Weebit was updated. Summaryof key changes to the license agreement are:
·Payment structure refined to reflect the current commercialisationschedule and the additional focus on the embedded memory market, as well asrevising the structure of royalties
·First annual minimum royalty payment delayed by one year from 1January 2019 to 1 January 2020 to reflect the current commercialisationschedule
The original Details on the Weebit licenceagreement are below:
(Fees and Royalties): Weebit is required to pay Rice University alicense initiation fee of $20,000 and the following royalties and fees:
1.royalties calculated at 1.5% onadjusted gross sales (sales of licensed products less costs attributable tosuch sales); and
2.25% of any cash or non-cashconsideration received as consideration under a sub-licence
(Annual Minimum Royalties): in addition to the above, Weebit willpay Rice University annual minimum royalties on the following milestone dates:
1.1 January 2019 - $10,000;
2.1 January 2020 - $20,000;
3.1 January 2021 - $100,000;
4.1 January 2022 - $250,000; and
5.1 January 2023 and each 1January of every year thereafter - $500,000, with each annual minimum milestonepayment creditable towards royalties due in the forthcoming year;
(First Commercial Sale): Weebit or a sublicensee will make a firstcommercial sale of a licensed product on or before 1 July 2019 and thereafterkeep available such licensed product for sale. Rice University may terminate orrender the agreement non-exclusive at any time after 4 years from the executiondate of the Rice University License Agreement if Rice University determine thatprogress reports do not demonstrate effective achievement of thecommercialisation of the licensed products;
GLA
(20min delay)