If you say so. Complex material effects are a little more, how can I say it, complex, than that. Its not simply a matter of "dialling back" X to get Y if one parameter is deficient.
In the case of endurance, the level is suitable, so you can shift the emphasis to read speed. But when something is coming up short, and I am not saying it is necessarily for retention, then that's a harder ask.
Slowing read speed down doesnt necessarily equate to better retention. More likely to be write speed since the write parameters would likely impact the retention, not necessarily the read. It may, but that depends on how the MOTT effect behaves when charge is applied or read is done. For instance, is a larger charge applied for longer associated with a longer retention in the cell? Does read reduce the retention? I dont know, is the read non-disruptive to the cell integrity?
And you are right, it does take time and money, but 4DS should be in the optimisation phase now and therefore should have the tweaking part funded already since its a known required phase to all chip development. Why they reported each wafer release result is beyond me, since most other chip developers wouldnt have.
I wont engage here too much, I'd only be called out as a holder of that other stock that shall not be named or accused of down ramping and I actually hope everyone does exceptionally well here.
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