This is Intel's patent application for in-memory SNNs:
US2019005376A1 IN-MEMORY SPIKING NEURAL NETWORKS FOR MEMORY ARRAY ARCHITECTURES
https://worldwide.espacenet.com/patent/search/family/064738229/publication/US2019005376A1?q=US2019005376A1a chip that includes a memory array having a plurality of rows corresponding to neurons in a spiking neural network (SNN) and a row decoder coupled to the memory array, wherein the row decoder activates a row in the memory array in response to a pre-synaptic spike in a neuron associated with the row. Additionally, the chip may include a sense amplifier coupled to the memory array, wherein the sense amplifier determines post-synaptic information corresponding to the activated row. In one example, the chip includes a processor to determine a state of a plurality of neurons in the SNN based at least in part on the post-synaptic information and conduct a memory array update, via the sense amplifier, of one or more synaptic weights in the memory array based on the state of the plurality of neurons.
1 . A chip comprising:
a memory array including a plurality of rows corresponding to neurons in a spiking neural network (SNN);
a row decoder coupled to the memory array, the row decoder to activate a row in the memory array in response to a pre-synaptic spike in a neuron associated with the row;
a sense amplifier coupled to the memory array, the sense amplifier to determine post-synaptic information corresponding to the activated row; and
a processor including logic coupled to the sense amplifier, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the sense amplifier to:
determine a state of a plurality of neurons in the SNN based on the post-synaptic information; and
conduct a memory array update, via the sense amplifier, of one or more synaptic weights in the memory array based on the state of the plurality of neurons and a learning heuristic, wherein the memory array update is to bypass off-chip communications.
A sense amplifier suggests to me memristor/ReRAM, despite the fact that the description has a catch-all paragraph:
[021] ...
A memory device may also include future generation nonvolatile devices, such as a three dimensional (3D) crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use silicon-oxide-nitride-oxide-silicon (SONOS) memory, electrically erasable programmable read-only memory (EEPROM), chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device ...
... and any other Buck Rogers tech you can think of.
Intel's Loihi 2 makes provision for up to 32-bit calculations, so it is a much bigger neural processor. This would provide greater precision than Akida (max 4-bit). On the other hand, the more bits it uses the slower and more power hungry the circuit would be. However, Loihi 2 can also use single bit spikes. I suppose that this gives them the flexibility to try different configurations.
Peter and Anil have gone to having a selection of 1-bit to 4-bit weights/activations, and they consider that this is adequate for the intended applications of Akida.
(20min delay)