Qualcomm to Buy NXP Semiconductors in $47 Billion Deal, page-9

The good news is you get your doctorate in e-archeology,

i.MX 93 uses ARN Ethos U65, which includes a microNPU (Neural Processing Unit)

There's lots to like:

Wake word detection - we have a patent application for this
ML

LSTM
pooling
activation functions

https://www.nxp.com/company/about-nxp/nxps-i-mx-93-applications-processor-family-powers-a-new-era-of-secure-edge-intelligence:NW-NXP-I-MX-93-APPLICATIONS-PROCESSOR-FAM
NXP’s i.MX 93 Applications Processor Family Powers a New Era of Secure Edge Intelligence
Nov 9, 2021 3:00 AM EST

i.MX 93
https://www.nxp.com/docs/en/fact-sheet/iMX93-FS.pdf

NEURAL PROCESSING UNIT (NPU)
The i.MX 93 family marks the industry’s first implementation of the Arm® Ethos™-U65 microNPU. A dedicated neural
processing unit (NPU), Ethos-U65 delivers a combination of performance and efficiency with an optimized footprint
that enables developers to create high-performance, costeffective and energy-efficient ML applications.

BUILT-IN MCU
A 250 MHz Arm Cortex-M33 processor performs time-critical real-time compute and control. It can eliminate the need
for an external microcontroller in the system design. The integrated Cortex-M33 core associated with the CAN FD
interfaces provides a robust local control network for industrial applications. Additionally, the built-in Arm Cortex M33 in
conjunction with the NPU can be used for low-power wakeword detection.

CAMERA INTERFACES AND IMAGE PROCESSING
The i.MX 93 family contains MIPI-CSI and parallel image sensor interfaces along with the NPU to support both monochrome and RGB (color) vision applications. The application processor offers a 2-lane MIPI-CSI camera interface capable of supporting 1080-p60 resolution and enables direct connection to external camera module and ISP. The application processors offer capabilities including down scaling, color space conversion, de-interlacing, alpha insertion, cropping and rotation of images for machine vision and other ML-related applications.



Note: High efficiency NPU in ML and Multimdia section.

ARM-Ethos U65
https://armkeil.blob.core.windows.net/developer/Files/pdf/arm-ethos-u65-product-brief-v2.pdf

Future-Proof Operator Coverage
Heavy compute operators run directly on the micro NPU, such as convolution, LSTM, RNN, pooling, activation functions, and primitive element wise functions. Other kernels run automatically on the tightly coupled Cortex-M using CMSIS-NN.

Mixed Precision
Supports Int-8 and Int-16: lower precision for classification and detection tasks;
high-precision Int-16 for audio and limited HDR image enhancements.

Akida does not do 8-bit or 16-bit.