Claim 1 . A memory processing unit comprising: a plurality of memory regions; a plurality of processing regions interleaved between the plurality of memory regions, wherein one or more of the plurality of processing regions are configured to perform one or more computation functions; one or more communication links coupled between the interleaved plurality of memory regions and plurality of processing units, wherein the communication links are configured for moving data between non-adjacent ones of the plurality of memory regions or plurality of processing regions; and one or more centralized or distributed control circuitry configured to control data flow into each given one of the plurality of processing regions from a first adjacent one of the plurality of memory regions to a second adjacent one of the plurality of memory region.
[0048] Referring now to FIG. 21 , data transfer in a memory processing unit, in accordance with aspects of the present technology, is illustrated. Data flow between a plurality of processing cores 21 10-2130 and corresponding adjacent memory regions 2140, 2150 can be controlled utilizing handshaking rather than by a global controller. For example, a second processing core 2120 can wait until it receives a signal 2160 from a first processing core 21 10 indicating that the first processing core has valid data. When the second processing core 2120 receives the signal 2160 indicating that the first processing core 21 10 has valid data, the second processing core 2120 can copy 2170 the data from the first processing core 21 10 and begin performing the computation function of the second processing core 2120 on the data copied from the first processing core 21 10. The second processing core 2120 can also send a signal 2160 to the first processing core 21 10 indicating that it has copied the data from the first processing core 21 10. In response to the signal 2160 from the second processing core 2120, the first processing core 21 10 can begin processing new data. The use of handshaking to control data flow can simplify the pipeline operation of the plurality of processing cores 21 10-2130 and corresponding adjacent memory regions 2140, 2150. For example, with handshaking, a central control logic is not needed to keep track of stalls in various processing cores 21 10-2130.
It even comes with its own personal von Neumann bottleneck:
[0049] Referring now to FIG. 22, data transfer in a memory processing unit, in accordance with aspects of the present technology, is illustrated. Data flow between a corresponding adjacent memory region 2210 and a plurality of processing cores 2220-2250 can be controlled using an arbiter mechanism 2260 to facilitate the memory access. The arbiter 2260 can provide for access to a corresponding adjacent memory region 2210 by each of a plurality of processing cores 2220-2250 in turn.
... although I guess this is their attempt to provide a bottle opener, even if it is inadequately described ... In addition, the memory region 2210 can utilize a multi-bank architecture to facilitate access by the plurality of processing cores 2220-2250. Each bank can support access by a corresponding processing core, so that the plurality of processing cores 2220-2250 can access the memory region 2210 simultaneously.
Footnote:
The inventors all have the same address at the Office of Technology Transfer Ann Arbor MI, so I presume that they work for the Michigan Uni, which would explain how MemryX got their rapid start by buying in the tech, or, more likely, MemrX is a spin-off from the Uni.
MemrX have a couple of othe patents with common inventors for ... (drum roll) ... dot product multipliers using zero-bit skipping (a sparsity trick).
US10853066B1Memory processing units and methods of computing DOT products including zero bit skipping
US10998037B2Memory processing units and methods of computing dot products ... replete with ReRAM:
BRN Price at posting:
$1.43 Sentiment: Buy Disclosure: Held
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