4DS - Anything but Charting, page-23469

C'mon Hash - you are conveniently forgetting that DRAM needs high endurance because it is rewritten every 64 milliseconds regardless of whether the data changes because there's a tiny retention time in a DRAM memory cell.

If reducing energy demand through reducing frequency of refresh wasn't a priority, DRAM manufacturers wouldn't be implementing "refresh aware" DRAM, which lengthens the length of the refresh cycle for static data out to 256 ms (4 x 64) wherever possible.

The reality is most data in active memory does not change that frequently. Even if memory was refreshed once a second for 10 years (which is working the cache HARD) that is:

3.2 x 10⁸ write cycles - using the endurance of 1 billion read/write cycles quoted by Acca above (times 2 - 3 equals 3 x 10⁹), that is still one order of magnitude LESS than the indicated endurance limit.

Power savings are absolutely a strong enough argument - the amount of DRAM that systems need continues to increase to keep performance at the bleeding edge - you can't just keep making cooling systems larger and larger to deal with the demands, everything needs to be engineered bigger - grid interconnect, water/cooling tanks.

If power savings weren't an argument - companies like Airlines and Mining Companies that use huge amounts of energy wouldn't obsess over every energy gain.