@StopTalking
same page - apologies for the length of this post in advance
Endurance / speed
what is more important than endurance ( as vital a metric as this obviously is) remans the threshold at which the resistance window collapses and endurance degradation / partial failure occurs....
this question will sit foremost on the table of any negotiation .....known or unknown......numbers are great but this will remain an unknown until a technology transfer occurs and results are on commercial foundry spreadsheet .....R&D metrics are fine but restrictively limit the 'deal' in the acquirers favour.....indeed 'at a discount'...it is not DRAM and the extent to which it will augment DRAM will also remain unknown until the test bench in the acquirer's 'shop' works some tape
( for those interested this is absolutely killing it - Micron gaining ascendency in the cartel card room)
https://venturebeat.com/2021/06/01/...-and-1-alpha-dram-chips-for-the-data-economy/
(Microns Universal Flash Memory version 1 ....version 2 on the way ( their description)....customers lining up out the door and around the corner )
Why?
programming conditions will need established and adjusted to achieve
endurance optimisation....this is the comment referenced in relation to smart algorithmic optimisation which potentially may see improved endurance performance.....but it will remain a discount card for the acquirer until it is in their foundry wafered and packaged off their equipment ( unless the company 4DS intend doing this off their own shiny new office machine in fremont.???)....we don't know
Endurance degradation failure follows a simple lognormal law (immutable really) with the cycle number and is engineered to the specific 'commercially viable' array....and that' just a simply fact in the 'trade off' .....that's what it means -
it is characterised within the very nature of resistive ram - an R&D version is a 'test pattern' but not reason for some large exchange of green.....complete this process in the acquirers foundry on a 'promisory note' of success and match that with their DRAM product ( and you have to hope that's who comes knocking because at this stage its damned if they do or don't - if its not a DRAMer it will be heavily discounted ....if it is a DRAMer the above must be satisfied on their foundry equipment before a large exchange of green ? ...No? that will be a term of acquisition or its not fair dinkum.... and it really needs to be a DRAMer imo ) ..
perhaps I have this wrong ?....i can only speculate like anyone else.
No empirical testing evidence exists on performance consequences of such a process in acquisition - its the nature of the process - Im assuming the fee charge from IMEC is to facilitate this process into the acquirers operation....it must be ? who else will do it ?
Untrained personnel in the acquiring organisation ? never seen that before ...maybe others have .....Team IMEC will need to do it ???
of course it must be them...who else knows it this well - acquire this and be 'slowed' to production through poorly characterised in foundry processes on a new product instigating new design flow = cost profit penalty......(plenty more to add but this post is getting too long)
it remains
a risk - particularly with new materials and new process design ....no matter how CMOS friendly ....again a simple reality...
.cost per bit yield will be the driver of a great opening to any negotiation no? that is the commercial collateral needed....commercial $$$$$ is the key word ...no cost benefit across 10yr time horizon to offset acquisition transfer investment ....discount card in play
suspect that will be the very first question ...no? it would be the first bullitt point on my sales brochure
why dribble on about this and that if its not cost per bit / yield competitive ?
again we don't know - it can't be released tomorrow because no one knows .....
So an endurance number alone is terrific and says volumes about potential underlying commercial viability .....but that is a discount card without the proven endurance degradation mitigation set out above aligned to a DRAM ....
Speed is great - near DRAM ...great
as endurance has mitigation trade offs so programming speed degrades retention
the punter and the acquirer know none of this - that 'mat' has to work on the IMEC 1MB array vehicle
that leads to another great announcement that 1MB is successful (potentially) and significant interest is garnered
the above regarding Endurance / speed will be 'tuned' down the track by the potential acquirer aligned to their DRAM ...
so it will remain unknown till that occurs ....it wont be even a conversation on the negotiation table because all parties concerned simply can't negotiate on unknowns .....discount card still in play
Ace in the hole - IMEC endorsed operational 'mat' and great cmos transferability data for an operational 1MB array in their test vehicle -
the punter needs to consider these simple bench fundamentals when ruminating on the possible acquirer and the potential green exchanging hands .... Id'e like to see PL4 but we all have our wish list
smarter people here than me so it is just my take on current state of play in all the noise here atm
im not suggesting this or that in opposition to any other posters opinion .....because that is all any of us have and know till 4DS reveal the tell!
bring on the next bit of news when we can all make a more informed decision if the company decide to make it known ....it does need to be more than 'array vehicle 1MB test successful' imo ...because it is expected and has been for some time
glah
(20min delay)