Ann: Company Update, page-9

Good to see they have a plan (of sorts). One concern I have is that they're trying to do too many things at once (someone here has mentioned something similar before). They think the problem is that the new etch process has damaged the PCMO layer so they are going to further optimize the etch process to fix this. They could just do this but they are also:

• planning "to explore optimized programming conditions to improve both the endurance and retention of 4DS Interface
  Switching ReRAM cells", and
• incorporating "additional improvements to the memory cell that were demonstrated on wafers
  processed at the Stanford Nanofabrication Facility will be incorporated in this next Platform Lot, as well"

Is this really necessary? Can't they eliminate the etch problem, then make these improvements? Concerned introducing too many factors could raise new issues.