Interesting link.
The presentation was largely over my head. However, the take-home is that they have gone to a lot of trouble to eliminate the von Neumann CPU-memory bottleneck, thereby improving speed and efficiency 10-fold. They have achieved this by creating the worlds largest ever chip, equal to the largest square that can be cut from a 300mm wafer (i.e. 300mm across the diagonals) which delivers "cluster-level compute" from a single device. It is comprised of a vast array of small processor cores co-located with their respective RAM (using SRAM to match the speed of the core), and is intended for use in data centres to run large neural networks.
Mind boggling, but still not a touch on would be possible using WBT's technology in a multilayered memristive neural network.
Weebit - 2023 and beyond, page-1555
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