A couple of issues at 60nm. It is a large chip and if you were to produce at that geometry the power demand for a commercial product would outweigh any advantages and with the large cell surface area, the heat generated by increased voltage and current would require large cooling capacity. 60nm is not commercially viable!
If people are looking at >Tbyte products then the geometry will need to be sub 20nm.
With the amount of mask’s required and the issue we have had getting this far and the issues with PCMO at lower geometries I would like to see what rabbit and what hat they intend to produce as an answer as any prospective buyer will want proof of scalability before purchasing.
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