Ann: Further Significant Megabit Success, page-950

A question I have regarding if a PL5 will go ahead is around 60nm megabit array. Negative posters have voiced issues on scaling lower, 4DS have said they can go to lower scale, but is this as small as IMEC test array will go to? So to this point there doesn't seem any reason to produce PL5 other than repeating PL4 with a few tweaks.
If this is the case then it's up to acquiring company to take this further.
Or can the chip be scaled lower but still combined on 60nm array.
( Sorry if this is a dumb question I'm an electrician only wire things together not make them )