Flectional3,846 Posts. 732424/09/2313:21Post #: 69998357Share@darrenrrthat is not correct at all compatible with lowest geometries is correct however....It will not scale to those material compatible geometries - etch rate fluctuations occur due to the insufficient amount of photo resist....this pushes the geometry up ...in 4DS case to 60nm to allow dry etch with hard mask this has allowed the megabit success which is great.Smaller geometries are not achievable at this point in time. the performance of the cell is still being characterised at 60nm and it is a working cell at this point - not a packaged wafer ...far from it.you will remember the “blocked etch metal island,” encountered by PL3 ...this is a direct result of the process I have described.furtherit is important to understand the behavior of these defect adders within the etching process sequence.Among these defect adders, post hard-mask etch residue is commonly observed after the oxide hardmask patterning followed by resist ashing and wet stripping.Such defect formation is found strongly related to the ashing process temperature as you scale the node....pretty simple to understand.there is plenty on the web to back this up - it is not merely my opinion.The discussions with IMEC and 4DS into a bilateral agreement to manufacture OR acquire will revolve around the potential of a 60nmfunctional cell to augment a DRAM manufacturer sufficiently in providing revenue advantage on cost per byte production in available cell area in a killer application category.we all look forward to those discussions and the outcome. Last edited by
Flectional: Today, 13:22Need drives innovation and creates value WBT Price at posting: $3.35 Sentiment: None Disclosure: Held
NewBrentb1,172 Posts. 54424/09/2313:22Post #: 69998366Share4DS Would have known that IMEC testing would have been at 60nm prior to PL4, So why did they develop @ 40nm?With IMEC being a leading " R & D Nano Technology Innovation Hub" I would have thought that would be able to test at far lower geometries and as you say 22nm "Sweet Spot" where there is a lot of development and production being carried out.The company has previously misled the shareholders before and I am very skeptical in what they say. WBT,4DS,BRN,ANL,KEY,PGY,STX,TRT,CXO,IVZ,TEG,TPD,PCL,LOM,LTRWBT Price at posting: $3.35 Sentiment: Hold Disclosure: HeldNewhappydayz14,051 Posts. 49224/09/2313:26Post #: 69998407ShareIndeed, and it's going to be a bonza for 4DS. Next 2 weeks are going to be fun.WBT Price at posting: $3.35 Sentiment: None Disclosure: Held
NewFlectional3,846 Posts. 732424/09/2313:47Post #: 69998530ShareIndeed and there is no such product category in existence presently as it is not required by the DRAM manufacturers...superfluous you may say - this is now the issue to be addressed going forward - to develop the tech into a killer application other than DRAM augmentation as I do not believe that is where the market is - Dram manufacturers would have already addressed this direction - compute express link is now providing that very cost effective 'block' solution now so what to do?The pcmo cell has already proved itself with other manufacturers at 75nm ....no market application developed. is more coin spent in an attempt to address the scaling mask/photo resist scaling issues into the material compatible smaller geometries or is there a company that with IMECs assistance has expressed interest in the augmentation of their existing DRAM technology through further tech development and or straight acquisition now knowing further development costs will be incurred?interesting situation from here going forward.Look forward to the discussions and the outcome.Need
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