4DS - Anything but Charting, page-28429

@darrenrr
oddly enough the very issue apple ( and all of them) are working to solve is the dram bottle neck
the high performance bottleneck is due exactly to memory latency / i o latency as previous post discussed so you need to
1) partition data chunks to cache based on locality
2) exploit spatial locality
that means you need a reram 'tuned' to the dram ( applied current optimises latency to match dram performance match) that can read larger data chunks
why?
load increasing data throughput to dram ddr4. lpddr5 ....whatever it is.... and the result is a 25% dram performance drop ...25% is a significant overhead due to the rewrite the dram needs to complete under data throughputs of this nature - think of the market applications where this is the case

so if you have a reram 'tuned' to the dram latency at optimal performance that will mitigate that 25% overhead rewrite and provide optimal 'forward feed' of the data chunks to specified 'spatial locality' storage you have the killer application you are looking for.....minimal retention is needed in this application - that's a key point to pick up on in these network solutions where Nand is the storage solution of choice (4ds is not a competitve storage solution at this point and it doesn't need to be in this application

Again = that's one of the reasons DM or anyone - keeps stating flash is going nowhere....they mean Nand ...and it's a valid point

scaling to 20nm is a manufacturing experiment to see if wafer / cost yield can be achieved to make it attractive to the foundrys and device manufacturers- a cost production sweet spot = an ' area A class' die size you can stick with across multiple development iterations to maximise returns
eg

(2021 figures)
60/65nm is double the cost adoption .....its an additional impost and perhaps cancels out the adoption performance advantage ( not an order of magnitude cost improvement on volume against exisiting 'fixes') no thanks say the big boys .....happy with the poor fixes we have on the overhead issues - but hit 20nm and you have adoption cost benefit and cost removal of the poor system fixes in place and you have x2 magnitude energy saving....order of magnitude switching improvement ....etc etc ....

starts to make an adoption case for itself ....a killer application (@Nutsy yeah smart TV's and every application where increasing data throughput causes the dram 25% performance loss ) - minimal retention required in this solution

think this is the path and the application but guessing of course