consider as well perhaps the intent to punch this out at 20nm process node - there are multiple issues to overcome to successfully engineer the design variance required to manufacture a working cell/wafer/lot and for test to also succeed if the prior is achieved.
so this is far from 'in the hat' and punters should expect there will be issues that require TEM and a re work off that first 20nm run....it is ludicrous to think it will be spun out successfully on the first hit - so much the better if it does and that would be BIG news in all the ways one can imagine,but far from likely.
as previously discussed 'tuneable' = current adjusted to optimum latency next to the DRAM use application selected = minimal retention required essentially....
latest news and the testing results are fantastic as it is one step closer to meeting a killer use application category- plenty more steps ahead with undoubtedly a few stumbles
just another view to consider - nothing more
Ann: 4DS Achieves New Write Speed Milestone, page-229
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