4DS - Anything but Charting, page-30259

60nm success in no way suggests 20nm success off the bat- thats an important point to keep in mind

RTO temperature optimisation during manufacture will be needed to achieve optimal die yield - it is not realistic to expect the next platform lot to bring the sale dollars for acquisition from those interested parties - it will though certainly sharpen the focus on a new market solution in 4DS switch only memory.

die cracks in the run should be expected at 20nm till the process is refined -
ie- 'hairline' in the sidewall and field of the die as well as backside die cracks may pass electrical testing but will cause field failures - metal trace run across the die periphery will detect 'edge' failures BUT annealing cracks beneath the surface evade such detection. - these can lead to residue in the sidewall channels also but such residue is easily evident - or they can appear clean with zero side wall residue and only be discovered under operational test conditions ( automotive being a clear example)
I expect IMEC to carry out this testing and optimisation and implement in-line crack detection to match high volume manufacturing processes that acquirers will require - ie a proven solution that is part of the sale -
this is not a down ramp - it is the process the 20nm pcmo som lot will be subject to and must prove optimal yield and such a solution will be part of achieving optimal yield

the alternative is it comes out of the oven first time right free of issues of any kind, passes all electrical testing and accelerated application stress testing and is an immediate home run at the 20nm process node delivering optimal yield - this is possible of course, but unlikely

all imo as always and something to keep in mind as '20nm' bakes up and comes out of the oven