accompanying 'floor traveler report' from IMEC would have highlighted any issues at manufacture re 't test' or 'regression' test outcomes etc so it seems that is in good overall shape - no defects it seems or they would have announced it
last question from the floor is key imo as a use case ( additional to those already mentioned and not mentioned) AI HBM accelerator/buffer ....highlights advantage of partitioning endurance/retention within memory sets within the chip area ensuring quality data coherence at speed across cpu/gpu = $$$$$$
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(20min delay)