Ann: Infineon Design Agreement and Company Update, page-604

Thanks K.

i agree about clarity, it's clearly a writing style thing. Maybe the inner lawyer in DM writes the quick facts but clearly not so much spelling out the "so what" to an uneducated stock market.

We should probably expect a pack from PH to explain the new infineon phase (but I reckon I've worked it out - down the bottom).


On my on my fourth re-read this week, I think that they've actually written what the imec the shortfall is, granted it requires some careful consideration...

I read:
> the imec platform enables 4DS to "characterise" both PL5 & PL6 (i.e. tell them the performance characteristics).
> the imec platform has been useful for characterising the memory in 2023 / 2024
> they engaged infineon to design a platform to achieve area based interface switching.
>PL5 "testing and characterisation" is delayed because of equipment / repair issues.

I interpret:
> the limitation of the imec platform is that it can't do area based interface switching.
> Nothing to suggest the imec platform currently limits characterisation of performance metrics for PL5 or PL6 (if PL6 successful).
> they say imec platform has been useful during 2024 and testing PL5 was happening in 2024 so this statement means it is useful for that too.
> they have not highlighted a delay to PL5 testing or characterisation due to any issues in the platform lot.

So what:
The area based interface switching requirement is "unique" to 4DS. The imec universal memory platform (made for a broad industry) wasn't designed to achieve that specific requirement because it really is a new requirement.

The imec platform can still provide the interface switching capabilities they need, it just can only price the same programming current the entire chip. It is therefore still capable of enabling 4DS to test all the different upper/lower limits of the PL5 and PL6 characteristics (read/write speed, endurance, power, (dare I say it) retention, etc).

However, the imec platform can't vary the current being applied to different areas of the memory to test the performance of 4DS's area based capability. Hence Infineon have been engaged to kick off this next phase of the memory development.

The Infineon outcomes are not required to characterise PL5 or PL6 performance.

My views:
They talk about all phases in this annoucment:
Phase 1 (Stanford?): memory cell development - no read/write circuitry.
Phase 2 (imec): interface switching Re-RAM - read/write circuitry.
NEW Phase 3 (Infineon): Area based interface switching Re-RAM - area based read/write circuitry

Phase 3 is a value add AFTER PL6 and is required to demonstrate the full potential of the unique area based characteristic.

Phase 3 does not hold up PL5 or PL6, but aspects of it can run independently and concurrently.

Having a phase beyond PL6 is a good strategy - it can demonstrate to a potential buyer there is further value to unlock, so why not buy now (i.e. after PL6 results).

there is food news just around the corner in two tranches PL5 and fingers crossed that PL6 was able to be successfully scaled (again the need for Infineon is in no way tied to PL6, so there is no change to the risk of scaling based on this annoucment).