i think that if imec has read/write circuitry that works on the memory at both 60nm and 20nm we can assume Infineon can create the area based read/write circuitry at both scales.
This is why infineon are able to start before PL5 results and PL6 is out of the oven... PL4, a working 60nm example, is enough for them to work with to make a start.
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