And as we know Brainchip is partnered with Andes Technology which holds 30% of the RISC-V market not to mention Brainchip’s earlier partnership with SiFive:
Laguna Hills, Calif. – April 23, 2025–BrainChip Holdings Ltd(ASX: BRN, OTCQX: BRCHF, ADR: BCHPY), the world’s first commercial producer of ultra-low power, fully digital, event-based, brain-inspired AI, today announced the integration of its NPUs with RISC-V cores from Andes Technology, the industry leading provider of RISC-V embedded cores. The companies will demonstrate BrainChip’s Akida™ AKD1500 on Andes’ QiLai Voyager Board and AndesCore™ AX45MP 64-bit multicore CPU IP at Andes RISC-V Con 2025 in San Jose, Calif. April 29 and in Hsinchu, Taiwan June 10.
The AKD1500 demonstrates the benefits of Akida’s pure digital, extremely energy-efficient, event-based AI computation for at-sensor or sensor-balanced solutions for AI, application processors, automotive electronics and security markets. The QiLai SoC and the Voyager development board further accelerates the development and porting of large RISC-V applications. Integrating BrainChip’s Akida technology and Andes’ high-performance QiLai SoC and Voyager development board provides a highly efficient solution for integrated edge AI compute and further expands the RISC-V ecosystem.
The Brainchip AKD1500 device is integrated into the Voyager development board using an M.2 card form factor. It delivers over 0.7 TOPS of event-based computing while consuming less than 250mW, achieving performance comparable to conventional CNN processing using 3–10× less compute. This demonstrates a cost and power-efficient path for integrating RISC-V SoCs, operating at a fraction of the power required by traditional AI accelerators. Akida is an event-based technology that is inherently lower power than conventional neural network accelerators, providing energy efficiency with high performance for partners to deliver AI solutions previously not possible on battery-operated or fan-less embedded, edge devices.
The Andes QiLai SoC chip incorporates a high-performance quad-core RISC-V AX45MP cluster. The AndesCore AX45MP is a superscalar, multicore design featuring a shared Level-2 cache, a coherence manager and a Memory Management Unit (MMU) to support Linux-based applications. Equipped with IOCP (I/O Coherency Port) interface, the AX45MP enables external hardware DMA to interact directly with the cache/memory subsystem, facilitating seamless communication between the AX45MP and high-speed modules like NPUs, GPUs and Gigabit Ethernet. Built on TSMC’s 7nm process technology, the AX45MP achieves clock speeds of up to 2.2 GHz on QiLai SoC. With higher Specint2006 performance than Cortex A55, high-clock frequency and multi-core Linux capabilities, the AX45MP has been very popular as Linux AP on various applications.
“We consistently search for ways to grow adoption of RISC-V solutions across an ever-increasing number of use cases,” said Dr. Charlie Su, CTO and President at Andes Technology. “By working with BrainChip and integrating the Akida IP into our QiLai Voyager platform, we better enable developers with opportunities to develop RISC-V-based solutions optimized for edge AI workloads and capabilities.”
“As a pioneer in ultra-low power AI processing, our Akida technology integrates with RISC-V to enable efficient, intelligent compute at the edge,” said Steve Brightfield, CMO at BrainChip. “Showcasing these attributes through the integration of the AKD1500 with Andes QiLai platform at RISC-V Con 2025, ideally demonstrates how these solutions can be used in production SoCs to provide next-generation breakthroughs.”
Andes RISC-V Con 2025 brings together developers and technologists from around the world to discuss advancements in RISC-V technology, exchange ideas and collaborate on the future of open computing architectures. BrainChip will showcase its latest innovations in ultra-low power AI solutions, demonstrating how its technology enhances edge computing applications. Attendees are invited to visit the BrainChip booth and attend the presentation to learn more about the role of AI acceleration in RISC-V-based designs. Interested parties can visithttps://bit.ly/brainchip-andesto register.
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