Lou once said reducing the silicon size will reduce power...

Lou once said reducing the silicon size will reduce power consumption and improve speed. However, a limiting factor on the overall package size may be the pin-out array (still requires the same number of pins) and the question of aligning the "pins" with the connecting pads. The physical alignment of the package must ensure the correct connections are made.
I also have a vague recollection that 28 nm has advantages for the radiation hardened version in decreasing the probability of tunneling of extraneous particles.
However, in the fullness of time, I expect we will see Akida 2, 3, 4 etc. coming out in the smaller architecture.