2020 BRN Discussion, page-26114

The Renesas R-Car-H3 Automotive SoC dates from 2015.

As previously discussed/speculated, the next generation (R-Car-H4?) may include Akida.

One potential area where Akida could be used is in image recognition.

In 2015, Renesas image recognition processor was their IMP-X5.

https://www.renesas.com/sg/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support

R-Car-H3 High-end Automotive System-on-Chip (SoC) for In-vehicle Infotainment and Driving Safety Support

Specifications:
...
High performance real-time image recognition processor (IMP-X5)

https://www.eenewseurope.com/news/third-generation-renesas%E2%80%99s-r-car-soc-targets-autonomous-driving

The on-chip IMP-X5 parallel programmable engine offers advanced image recognition technology in addition to the CPU and GPU. Exclusive to Renesas, the IMP-X5 recognition engine is optimized for interoperation with the CPU. It delivers four times the recognition performance of the earlier IMP-X4 image recognition engine, embedded in the second-generation R-Car family.

However, in March 2018, they upgraded their imaging system to stereo vision.

https://innovation-destination.com/2018/03/29/dual-camera-capable-soc-steps-up-adas-vision-systems/

The R-Car V3H is Renesas latest automotive power house designed to meet automotive ISO 26262 standards.
By William Wong, Senior Technology Editor

Image recognition using two cameras for stereovision is one way to identify the location and type of object in view. This form of vision processing is very useful for advanced driver-assistance systems (ADAS), including support for self-driving cars. Foresight’s QuadSight vision system actually uses a pair of stereovision systems. One uses the visible spectrum while the other uses infrared.

Renesas’ new R-Car V3H system-on-chip (SoC) targets this space with support for dual cameras, including a dual image signal processor (ISP) and two channels of four MIPI-CSI2 lanes (Fig. 1). This is augmented with the IMP-X5-V3H image-recognition engine.

There’s also dedicated hardware accelerators for convolutional neural networks (CNN), dense optical flow, stereovision and object classification.

The SoC is built around a pair of Arm multicore blocks. The main processor is a 1-GHz, quad-core, Cortex-A53 MPCore. The real-time processor is a dual, lockstep 800-MHz Cortex-R7 (Fig. 2). The system has a single-channel, 32-bit memory controller that can handle LPDDR4-32000. The system also features LVDS display support, a gigabit Ethernet port, and a AVB Ethernet port, as well as a x2 PCI Express port. Other digital interfaces include dual FlexRay support, CAN and CAN FD support, UARTs, SPI, and I2C.

The R-Car V3H includes a 1-GHz, quad-core Arm Cortex-A53 along with a dual, lockstep 800-MHz Arm Cortex-R7. There is also dedicated hardware for stereovision and convolutional neural network (CNN) support.

Versions are available without the vision support. The SoC is designed to deliver high performance with low power consumption. It targets ADAS systems that handle lane keeping, road-sign detection, and emergency braking, in addition to being used in self-driving vehicles. It’s designed to meet the New Car Assessment Program (NCAP) regulations.Renesas is partnering with companies like Synopsys to deliver computer-vision capabilities for smart cameras in Level 3 and Level 4 autonomous vehicles. Synopsys provides an extensive portfolio of certified tools and flows to help developers deliver safety-related ASIL A through ASIL D designs using the R-Car family. This includes taking advantage of the CNN and vision processing support.

Given that the new Renesas system uses CNN, Akida would fit right in.