Here are a few Renesas Ai related patent applications.
WO2020038551 is a joint patent application with Bosch.
US2019384574 relates to DRPs.
I think they could all be improved by a touch of Akida.
WO2020038551A1 CONVOLUTION-BASED PROCESSING
Applicants BOSCH GMBH ROBERT [DE]; RENESAS ELECTRONICSCORP [JP]
Inventors BUCHHOLZ JAN [DE]; KOEHLER ROLF [DE]; NAHR MATTHIAS [DE]; PETRIZIO PIA [DE]
Priorities EP2018072455W·2018-08-20 Application EP2018072455W·2018-08-20
Publication WO2020038551A1·2020-02-27
Published as WO2020038551A1
Abstract Apparatus is disclosed comprising a hardware processing module and an external memory controller coupled to the hardware processing module. The hardware processing module comprises an input memory controller configured to receive data from the memory controller, a set of convolution units each convolution unit capable of performing a convolution on a respective portion of the data using a filter having size u x v, wherein u and v are each a positive integer equal to or greater than one, and an output memory controller configured to output data derived from the convolution units. The data is divided or divisible into k channels, where k is an integer greater than or equal to two. The apparatus is configured to provide interleaved lines of the data, sequentially interleaved from the k channels, to the input memory controller.
EP3576022A1 SEMICONDUCTOR DEVICE AND MEMORY ACCESS SETUP METHOD
Applicants RENESAS ELECTRONICS CORP [JP]
Inventors LIESKE HANNO [JP]; MATSUO SHIGERU [JP]; NAKAMURA ATSUSHI [JP]; SASAMOTO MANABU
Priorities JP2018101344A·2018-05-28
Application EP19175054A·2019-05-17 Publication EP3576022A1·2019-12-04
Published as CN110543938A;EP3576022A1;JP2019207458A;US2019361620A1
Abstract Limitations on memory access decrease the computing capability of related-art semiconductor devices during convolution processing in a convolutional neural network. A semiconductor device according to an aspect of the present invention includes an accelerator section that performs computation on a plurality of intermediate layers included in a convolutional neural network by using a memory having a plurality of banks capable of changing the read/write status on an individual bank basis. The accelerator section includes a network layer control section that controls a memory control section in such a manner as to change the read/write status assigned to the banks storing input data or output data of the intermediate layers in accordance with the transfer amounts and transfer rates of the input data and output data of the intermediate layers included in the convolutional neural network.
US2020210820A1 SYSTEM AND METHOD FOR MACHINE-LEARNING
RENESAS ELECTRONICS CORP [JP]
Inventors WAKAYAMA YASUSHI [JP]
Priorities JP2018243998A·2018-12-27
Application US201916709670A·2019-12-10 Publication US2020210820A1·2020-07-02
Published as CN111382866A;JP2020107012A;US2020210820A1
Abstract A processing system includes a receiving circuit 1 for receiving an input signal from an externally connected sensor, an expected signal generating circuit 4 for automatically generating a teaching signal for use in the learning circuit 5, a learning circuit 5 for calculating a weight value, a bias value, and the like of the neural network model to form an expected signal from the teaching signal generated by the expected signal generating circuit 4 and the signal from the receiving circuit 1, an inference circuit 2 for performing signal processing based on a learned model of the neural network model generated by the learning circuit 5, and a validity verification circuit 3′ for performing similarity calculation between an output signal of the inference circuit 2 and an expected signal for comparison.
US2019384574A1 SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SEMICONDUCTOR DEVICE
Applicants RENESAS ELECTRONICS CORP [JP]
Inventors FUJII TARO [JP]; TANAKA TERUHITO [JP]; TOGAWA KATSUMI [JP]; TOI TAKAO [JP]
Priorities JP2018114861A·2018-06-15
Application US201916410825A·2019-05-13 Publication US2019384574A1·2019-12-19
Published as CN110609804A;JP2019219753A;US2019384574A1
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SEMICONDUCTOR DEVICE
Abstract
A semiconductor device includes a dynamicreconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.
(20min delay)