Looking into the ReRAMto catch up a bit, and found a few things, maybe a couple of otherson here could add to.
Regarding ReRAM beingproduced in a stadard CMOS process, I found this article stating:
“Weebit’s silicon oxide ReRAM uses standard materials that easily fit into existing production lines. “We’ve seen that we can manufacture it with just one or two added masks.”
And...
" Both ReRAM and STT-MRAM require only a few mask steps and are manufactured in the so-called backend-of-the-line (BEOL) in a fab. And both STT-MRAM and ReRAM are built on top of a contact or via at one of the metal layers of a chip. "
Therefore it is extraprocesses and not scalable?
RE:
"Some MTP NVM will work with a standard CMOS process, whereby no extra steps or masks are involved. Instead, it can be manufactured using a standard CMOS process, which means it can continue to be scaled. But the MTP version requires a floating gate, like a flash cell. "
Found this relating to 5G as well:
https://semiengineering.com/automakers-changing-tactics-on-reliability/
and a new RAM to replace ReRAM / FeRAM / PCM (3D XPoint) / FeFET
https://www.extremetech.com/computing/304980-scientists-may-have-discovered-universal-memory-dram-replacement
2020 BRN Discussion, page-404
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