Meanwhile, over at Weetbix: US10650308 discussed STDP and ReRAM....

Meanwhile, over at Weetbix:
US10650308 discussed STDP and ReRAM.

https://patents.justia.com/patent/10650308

Electronic neuromorphic system, synaptic circuit with resistive switching memory and method of performing spike-timing dependent plasticity
Patent number: 10650308
Abstract: A synaptic circuit performing spike-timing dependent plasticity STDP interposed between a pre-synaptic neuron and a post-synapse neuron includes a memristor having a variable resistance value configured to receive a first signal from the pre-synaptic neuron. The circuit has an intermediate unit connected in series with the memristor for receiving a second signal from the pre-synaptic neuron and provides an output signal to the post-synaptic neuron. The intermediate unit receives a retroaction signal generated from the post-synaptic neuron and the memristor modifies the resistance value based on a delay between two at least partially overlapped input pulses, a spike event of the first signal and a pulse of the retroaction signal, in order to induct a potentiated state STP or a depressed state STD at the memristor. An electronic neuromorphic system having synaptic circuits and a method of performing spike timing dependent plasticity STDP by a synaptic circuit are also provided.
Type: Grant
Filed: September 23, 2015
Date of Patent: May 12, 2020
Assignee: POLITECNICO DI MILANO
Inventors: Daniele Ielmini, Simone Balatti, Stefano Ambrogio, Zhongqiang Wang

Fairly narrow claim 1 based on memristor:

https://worldwide.espacenet.com/patent/search/family/058282521/publication/US10650308B2?q=us10650308

Claim 1: A synaptic circuit performing spike-timing dependent plasticity (STDP) interposed between a pre-synaptic neuron and a post-synapse neuron and comprising:

a memristor having a variable resistance value (R) and being configured to receive a first signal (V TE) from the pre-synaptic neuron;

transistor structure connected in series with the memristor and being configured for receiving a second signal (V CG) from the pre-synaptic neuron and being configured for providing an output signal (I BE) to the post-synaptic neuron,

wherein the transistor structure is further configured to receive a retroaction signal (V FG) generated from the post-synaptic neuron, and

the memristor is configured to modify the resistance value (R) based on a delay (Δt) between two at least partially overlapped input pulses, a spike event (F E1) of the first signal (V TE) and a pulse (V FGMAX) of the retroaction signal (V FG), in order to induct a potentiated state (STP) upon a decreasing the resistance value (R) and a depressed state (STD) upon increasing the resistance value (R) at the memristor, and

wherein the transistor structure comprises a first transistor and a second transistor that are connected in parallel and are interposed between a first inner node and a second inner node of the transistor structure, the first transistor having a control terminal coupled to the pre-synaptic neuron for receiving the second signal (V CG) and the second transistor having a control terminal connected to the post-synaptic neuron for receiving the retroaction signal (V FG), and

wherein the memristor is a two terminals memristor interposed between the first input terminal and the first inner node.