As to SRAM, see:
https://worldwide.espacenet.com/patent/search/family/070850826/publication/WO2020112485A1?q=WO2020112485A1
WO2020112485A1 SRAM-BASED PROCESS IN MEMORY SYSTEM - UNIV MICHIGAN REGENTS
SRAM-BASED PROCESS IN MEMORY SYSTEM
Abstract
Many signal processing, machine learning and scientific computing applications require a large number of multiply-accumuiate (MAC) operations. This type of operation is demanding in both computation and memory. Process in memory has been proposed as a new technique that computes directly on a large array of data in place, to eliminate expensive data movement overhead. To enable parallel multi-bit MAC operations, both width- and level- modulating memory word Sines are applied. To improve performance and provide tolerance against process-voltage-temperature variations, a delay-locked loop is used to generate fine unit pulses for driving memory word lines and a dual-ramp Single-slope ADC is used to convert bit line outputs. The concept is prototyped in a 180nm CMOS test chip made of four 320x64 compute-SRAMs, each supporting 128x parallel 5bx5b MACs with 32 5b output ADCs and consuming 16.6 mW at 200MHz.
Some prior art from 2007 for compute-in-memory was cited:
Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells, or computing memory arrays (CAMs).
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