2021 BRN Discussion, page-17616

Not sure if this has already been posted but thought it may be an interesting read for some of the tech savy amongst us (myself not included). There is paper titled “A graph placement methodology for fast chip design” which can be accessed here(pdf) or on the link below, (Published online: 9 June 2021) which discussed the method currently used to design the next generation of Google’s AI chips.

https://www.nature.com/articles/s41586-021-03544-w.epdf?sharing_token=tYaxh2mR5EozfsSL0WHZLdRgN0jAjWel9jnR3ZoTv0PW0K0NmVrRsFPaMa9Y5We9O4Hqf_liatg-lvhiVcYpHL_YQpqkurA31sxqtmA-E1yNUWVMMVSBxWSp7ZFFIWawYQYnEXoBE4esRDSWqubhDFWUPyI5wK_5B_YIO-D_kS8%3D

Some things that I thought might be of interest:

• It talks about zero-shot mode (applying a pre-trained policy to a new netlist with no fine-tuning), which can generate a placement in less than a second on a single GPU.
• On page 211 it says " For our method, we use a policy pre-trained on the largest dataset (20 TPU blocks) and then fine-tune it on five target unseen blocks (denoted as blocks 1–5) for no more than 6h. For confidentiality reasons, we cannot disclose the details of these blocks, but each contains up to a few hundred macros and millions of standard cells.