2021 BRN Discussion, page-19679

Oops!

That drawing is from:

US2019026249A1 COMPUTATIONAL ARRAY MICROPROCESSOR SYSTEM USING NON-CONSECUTIVE DATA FORMATTING
https://worldwide.espacenet.com/patent/search/family/065019094/publication/US2019026249A1?q=US20190026249

In various embodiments, the data size of the processing elements of vector engine 111 is the same size or larger than the data size of the computation units of matrix processor 107 . For example, in some embodiments, computation unit 109 receives two operands each 1 byte in size and outputs a result 4 bytes in size. Processing element 113 receives the 4-byte result from computation unit 109 as an input 4 bytes in size.



The layout is similar to that shown in BJ65's earlier post. Note the massive heat sink arrangement.

BJ65

2 Posts.

20/08/21

02:34

Post #: 55430419