2021 BRN Discussion, page-21883

The is a constant background fear about China and how advanced it is in the race to Ai. I just happened upon the following article out of Hong Kong and before the leading academic who was interviewed for the article is arrested and the publisher closed down I copied it and now present it for consideration. It does of course not mention AKD1000 or Brainchip because it is about the Chinese Ai market. It is interesting however that @uiux has been finding all these links to US Department of Defence projects and Defence Contractors that on balance must be at least aware of Brainchip and its technology advances given that they are in a race to "rule the world" and where Ai will be the distributor of the spoils of war to the victor.

My opinion only DYOR
FF

AKIDA BALLISTA

Has the AI chiptransitioned from infancy to maturity?

2021/09/08 14:59:33HKT

As the cornerstoneof the development of the artificial intelligence industry, AI chips havedeveloped rapidly in recent years, and many companies have deployed one afteranother. Chips are systems engineering all the time, and high investment, highrisks, and slow returns are typical characteristics of the chip industry.

At present, whatmany companies do is to enhance intelligence instead of real artificialintelligence. It is still far from real artificial intelligence. Many people inthe industry have also said that the current development of AI chips seems tobe hot, but the global AI chip industry is still in Infancy", the futuredevelopment still needs to find a breakthrough point.

The processor chipsneeded in current security video equipment mainly include three types: SoCchips in the front-end IPC, SoC chips in the back-end DVR/NVR, and deeplearning algorithm accelerator chips. When faced with security scenarios, manychip companies have gradually discovered that the most critical part of thechip is not simply to increase the computing power. If storage optimization isnot performed, the actual computing power provided by the chip will be greatlyreduced.

Von Neumann'sbottleneck protrudes in AI applications

The challenge thatAI chips bring to traditional chips is not only in the computing architecture,but more in the storage architecture.

The traditionalchip uses the von Neumann architecture, in which the computing module and thestorage unit are separated in the core architecture. The CPU and the memorystick are not integrated, only a very small cache is set in the CPU.

In other words, theCPU must first read data from the storage unit when executing commands. Foreach task, if there are ten steps, then the CPU will read, execute, read, andexecute again ten times in sequence...This causes delay and a lot of powerconsumption is spent on data reading.

This problem isalso known as the "memory wall" problem of traditional chips.

In AI applications,von Neumann's "bottleneck" problem becomes more and more serious. Thealgorithm that AI relies on is a huge and complex network. There are manyparameters to store, and a lot of calculations need to be completed. Thesecalculations will generate a lot of data. In the process of completing a largenumber of calculations, the general chip design idea is to increase a largenumber of parallel computing units, such as thousands of convolution units, andthe storage resources that need to be called are also increasing.

It is not anexaggeration to say that although AI start-up chip companies adopt differentpaths to build chips, they are in fact trying to solve this problem. Most ofthe hardware architecture innovations proposed for AI, especially foraccelerating neural network processing, are fighting this problem.

Chipdemand, so many

With the rapiddevelopment of machine learning and other technologies, the development of theartificial intelligence industry is becoming a new important economic growthpoint with its high-end emerging technologies, huge commercial value, broadapplication prospects and huge industrial space. With the popularization anddevelopment of various application scenarios of artificial intelligence,massive multi-dimensional data will be processed and calculated in the cloudand on the edge side. Chips are also facing more extensive and diversifiedneeds, which will affect the computing architecture, computing power, andScenarios and algorithm applicability, security and controllability, etc. allpose new issues and challenges.

At present, themainstream path of AI chip technology is GPU, FPGA, ASIC, etc. Among them, GPUand FPGA are relatively mature chip architectures, and ASIC is a dedicated chipfor specific application scenarios. GPU architecture chips can meet the massivecomputing needs of deep learning and unleash the potential of artificialintelligence, but the disadvantage is higher power consumption; FPGAarchitecture chips have sufficient computing power, lower trial and errorcosts, and sufficient flexibility, but the disadvantage is price High and complexprogramming; ASIC architecture chips can be enhanced in specific functions,with higher processing speed and lower energy consumption, but the disadvantageis that the cost is high, and the cost can be reduced when the useful amount islarge enough, and because it is customized , Reproducibility is general.

Traditional chipcompanies usually pay more attention to how to make chips universal to supporta variety of different application scenarios. However, such generalization willencounter problems when AI scenarios are implemented. For example, companiesconsider AI chips more per unit power consumption, and chip companies may nothave the primary priority on power consumption requirements. In the process ofimplementing AI scenarios, the company found that general-purpose chips couldnot meet the needs at all, which caused problems for companies engaged in AIsolutions and core algorithms-the company's algorithms are unified, but theyneed to be adapted in different scenarios Different chips and modules.

From theperspective of power consumption, many cloud-trained AI models cannot besuccessfully deployed to edge-side devices, and application scenarios cannotsupport high chip power consumption. Although some cloud chip giants are alsoextending to the edge, tailoring the AI algorithm to adapt the chip morereflects the limitations of the giants in cutting their feet and adapting totheir feet.

For example, in thefield of security, the main feature of data lies in the need to process a largenumber of continuous image data streams in real time. The first is that theprocessing frame rate per second is getting higher and higher, and the secondis that the image resolution is higher. In these two dimensions, higherrequirements are placed on edge chips. SoC is oriented to the dedicated market.In fact, the deep learning acceleration calculation in the chip is only a part,while most of the other chip area is handed over to the main control processor,video decoding and other modules. The application of the terminal general deeplearning accelerator chip market has just started. The market layout of manycompanies mainly focuses on cultivating developer ecosystems. On the otherhand, they are also exploring which field has the most potential, and launchingcorresponding optimized chips for several important scenarios. However, moreapplication scenarios are still facing coreless available state.

Severemarket bubble

The elements thatAI chips should have include programmability, dynamic variability of architecture,efficient architecture transformation capabilities, high computing efficiency,high energy consumption efficiency, and low cost. According to theserequirements, some of the current practices in the industry are not ideal.

Ni Guangnan, anacademician of the Chinese Academy of Engineering, said that the threshold forchip design is extremely high, and only a few companies can afford the R&Dcosts of mid-to-high-end chips, which also restricts innovation in the chipfield.

But "noindustry, no AI, no application, no AI, no chip, no AI" is the status quoof the current artificial intelligence boom. Although many companies focus onthe research and development of the underlying architecture of AI chips, thereare also many AI chip companies that "only pursue what is available, notgood," and use a patchwork method to make chips. Many companies packagethemselves as an AI chip company in order to comply with the market situation,and domestic AI chip companies generally lack back-end design talents.

Compared with thelogic design of the front-end, the back-end design is more related to theprocess of the chip, and relatively more experience is required. The domesticshortage of back-end design talents is even greater. Many AI chips currentlyused by enterprises are difficult to tape out on the mainland because of highprocess requirements, and they are all taped out at TSMC. At the same time, dueto the high complexity of the process, the price of chips is high, making manydownstream products that use its modules unable to be mass-produced. Therefore,many manufacturers will provide back-end services through outsourcing tocomplete production.

Therefore, in thecurrent domestic market atmosphere of AI chips, it has caused a lot of bubblesin the market.

Concludingremarks

There are two maintypes of companies in China that are currently players of AI chips. The firstcategory is not bad for money Internet companies, and the second category isunicorn companies.

However, thecharacteristics of the chip determine the speed of its advancement. It is stillin the incubation period. In the future, it is necessary to combine nationalpolicy support and innovation capital to achieve breakthroughs in the chipindustry chain and ensure the country's chip strategy security."

PS: Remember these sage words:

"Many companies package themselves as an AI chip company in order to comply with the market situation,
and domestic AI chip companies generally lack back-end design talents."

Brainchip is three years ahead of all the world even China.