I was of two minds whether to post here under general discussion or the competition thread however even though it mentions the competition it does so for the purpose of telling the world why Intel Loihi. IBM True North, Google TPU and NVIDIA CUDA GPU are just not up to scratch and why SNN is the ants pants. Problem might be for these little bunny rabbits is that though they come up with their own little SNN processor it is diminutive in comparison to AKD1000 and though they spend a significant amount of time speaking about Spike Time Dependant Plasticity rules they have failed to give any academic credit to the JAST boys.
Being concerned to promote academic integrity I have sent the reference off to Tony Dawe for the Brainchip Patent experts to have a look and take any action necessary given Brainchip has a granted patent in China and academic rules should be followed. .
https://www.mdpi.com/2079-9292/10/19/2441/pdfArticle A Low‐Cost Hardware‐Friendly Spiking NeuralNetwork Based on Binary Mram Synapses, Accelerated Using In‐Memory Computing
Yihao Wang, Danqing Wu, Yu Wang, Xianwu Hu, Zizhao Ma, Jiayun Feng and Yufeng Xie * State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 201203, China; [email protected] (Y.W.); [email protected] (D.W.); [email protected] (Y.W.); [email protected] (X.H.); [email protected] (Z.M.); [email protected] (J.F.) * Correspondence: [email protected]; Tel.: +86‐021‐5135‐5206
Abstract: In recent years, the scaling down that Mooreʹs Law relies on has been gradually slowing down, and the traditional von Neumann architecture has been limiting the improvement of computing power. Thus, neuromorphic in‐memory computing hardware has been proposed and is becoming a promising alternative. However, there is still a long way to make it possible, and one of the problems is to provide an efficient, reliable, and achievable neural network for hardware implementation. In this paper, we proposed a two‐layer fully connected spiking neural network based on binary MRAM (Magneto‐resistive Random Access Memory) synapses with low hardware cost. First, the network used an array of multiple binary MRAM cells to store multi‐bit fixed‐point weight values. This helps to simplify the read/write circuit. Second, we used different kinds of spike encoders that ensure the sparsity of input spikes, to reduce the complexity of peripheral circuits, such as sense amplifiers. Third, we designed a single‐step learning rule, which fit well with the fixed‐point binary weights. Fourth, we replaced the traditional exponential Leak‐Integrate‐Fire (LIF) neuron model to avoid the massive cost of exponential circuits. The simulation results showed that, compared to other similar works, our SNN with 1,184 neurons and 313,600 synapses achieved an accuracy of up to 90.6% in the MNIST recognition task with full‐resolution (28 × 28) and full‐bit‐ depth (8‐bit) images. In the case of low‐resolution (16 × 16) and black‐white (1‐bit) images, the smaller version of our network with 384 neurons and 32,768 synapses still maintained an accuracy of about 77%, extending its application to ultra‐low‐cost situations. Both versions need less than 30,000 samples to reach convergence, which is a >50% reduction compared to other similar networks. As for robustness, it is immune to the fluctuation of MRAM cell resistance.
Keywords: spiking neural network (SNN); binary MRAM synapses; spike‐rate neural coding; unsupervised learning; discretized spike‐timing‐dependent plasticity (STDP); leak‐integrate‐fire (LIF) model; in‐memory computing; hardware acceleration
1. Introduction With the development of artificial intelligence in recent years, the third‐generation artificial neural network (Spiking Neural Networks, SNNs) driven by spike events is gradually becoming a research hotspot. Compared with traditional artificial neural networks, the SNN has the advantages of higher computational efficiency and stronger biological rationality. Attempts to implement hardware‐accelerated spiking neuralnetworks have been made by academia and industry, such as IBM TrueNorth [1] andIntel Loihi [2]. The TrueNorth chip includes 1 million neurons and 256 million synapses within 430 mm2 under a 28 nm process. It features event‐driven, hybrid clock, near‐memory computing, and other technologies, consuming 65 mW of power typically. Loihi uses an on‐chip network for communication, whose neural cores are time‐division‐multiplexed to simulate each part of the neuron. The whole chip implements 128 neuromorphic cores on a single chip of 60 mm2. These two chips, as a representative of thetraditional CMOS implementation of a spiking neural network, have commonproblems: they simulate the mechanism of the brain only at the algorithm level,instead of using more efficient and biologically reasonable methods, which hascaused a high complexity and high cost of hardware design, and has limited theprocessing power because of the inherent bottleneck of Von Neumann architecture [3]
2.1.3. Learning Rule with Single‐step Fixed‐point WeightUpdate In the ANN, calculations involved in training include multiplication, addition, and derivation. In order to accelerate thesecomplex operations, various application‐specific integrated circuits (ASICs)have been proposed, such as Google TPU [25] and NVIDIA CUDA GPU [26]. Theseimplementations have been widely used because of their high Electronics 2021,10, 2441 7 of 16 performance, but there is a general problem of energyefficiency in these massive digital circuits
My opinion only DYOR
FF
AKIDA BALLISTA
(20min delay)